J4 ›› 2015, Vol. 42 ›› Issue (6): 113-117.doi: 10.3969/j.issn.1001-2400.2015.06.020

• 研究论文 • 上一篇    下一篇

沟道尺寸对深亚微米GGNMOS保护器件特性的影响

吴晓鹏;杨银堂;刘海霞;董刚   

  1. (西安电子科技大学 宽禁带半导体材料与器件教育部重点实验室,陕西 西安  710071)
  • 收稿日期:2014-12-31 出版日期:2015-12-20 发布日期:2016-01-25
  • 通讯作者: 吴晓鹏
  • 作者简介:吴晓鹏(1979-),女,西安电子科技大学博士研究生,E-mail: xpwu@mail.xidian.edu.cn.
  • 基金资助:

    陕西省科技统筹创新工程计划资助项目(2011KTCQ01-19);中央高校基本科研业务费专项资金资助项目(K5051325011)

Research on the influence of the channel dimension on the characteristics of the gate grounded NMOS protection device

WU Xiaopeng;YANG Yintang;LIU Haixia;DONG Gang   

  1. (Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an  710071, China)
  • Received:2014-12-31 Online:2015-12-20 Published:2016-01-25
  • Contact: WU Xiaopeng

摘要:

基于测试结果,研究了不同沟道宽度、沟道长度对深亚微米单叉指栅接地N型金属氧化物半导体静电放电保护器件性能的影响机制,并得出保护器件沟道尺寸的优化准则.基于SMIC 018μm CMOS工艺进行流片及传输线脉冲测试,得到了不同版图参数条件下保护器件的I-V特性.基于失效电流水平变化趋势以及器件仿真结果,分析了相关物理机制.研究结果表明,沟道宽度的选取必须结合器件的导通均匀性情况,同时沟道长度值则通过改变器件沟道下方的热分布影响保护器件的鲁棒性.利用实验方法分析了沟道尺寸对单叉指栅接地N型金属氧化物半导体保护器件性能影响的物理机制,对深亚微米保护器件的版图设计提供了优化指导.

关键词: 沟道宽度, 沟道长度, 静电放电, 栅接地N型金属氧化物半导体

Abstract:

The effect of the channel width and channel length on the single finger GGNMOS ESD protection device based on the deep sub-micron technology is researched, which gives the insight into the selection of the optimum value for the channel. The I-V characteristic of the protection device with various layout parameters results from the tapeout based on the SMIC 018μm CMOS process and the TLP test. The physics mechnism is detailed based on the variation tendency of the failure current level and the device simulation. The results show that the selection of the channel width should consider the on-off uniformity and that the channel length affects the robustness of the protection device by changing the heat distribution under the channel. This paper analyzes the physical mechnism of the effcts of the channel dimension on the single finger GGNMOS protection device and gives the guidauce for the optimum layout design of the deep sub-micron ESD protection devices.

Key words: channel width, channel length, electrostatic discharge, gate grounded negative channel metal oxide semiconductor