用于8位80MS/s模数转换器的增益数模单元电路

doi:10.3969/j.issn.1001-2400.2016.01.029

J4 ›› 2016, Vol. 43 ›› Issue (1): 162-166+172.doi: 10.3969/j.issn.1001-2400.2016.01.029

用于8位80MS/s模数转换器的增益数模单元电路

董嗣万;朱樟明;刘敏杰;杨银堂

(西安电子科技大学微电子学院，陕西西安 710071)

收稿日期:2015-03-17 出版日期:2016-02-20 发布日期:2016-04-06
通讯作者: 董嗣万
作者简介:董嗣万(1988-)，男，西安电子科技大学博士研究生, E-mail: dsiwan@163.com．
基金资助:
国家自然科学基金资助项目(61234002，61322405，61306044，61376033)

Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter

DONG Siwan;ZHU Zhangming;LIU Minjie;YANG Yintang

(School of Microelectronics, Xidian Univ., Xi'an 710071, China)

Received:2015-03-17 Online:2016-02-20 Published:2016-04-06
Contact: DONG Siwan

摘要/Abstract

摘要：

提出了一种针对高速中精度模数转换器的增益数模单元电路优化设计，满足8位80MS/s流水线模数转换器的要求．通过优化设计一种改进传输门开关，提高了增益数模单元电路的线性度；针对高增益两级宽带运算放大器，提出了一种宽带运算放大器优化设计方法，能有效地优化运算放大器的建立时间和功耗；优化设计了一种高速低功耗动态比较器，在提高速度方面具有优势．基于0.18μm 1.8V CMOS工艺完成了增益数模单元及8位80MS/s流水线模数转换器的流片验证，测试结果表明，在80MHz采样频率下，输入信号频率为35MHz时，模数转换器的信号噪声失调比为 48.9dB，有效位数为7.83位．

关键词: 增益数模单元, 运放优化, 传输门, 动态比较器, 流水线模数转换器

Abstract:

A high speed and medium accuracy multiplying digital-to-analog converter (MDAC) circuit optimization design is presented for meeting the requirements of the 8bit, 80MS/s pipelined analog-to-digital (A/D) converter. An optimized transmission gate is adopted to improve the linearity of the MDAC circuit. In view of the high gain two-stage operational amplifier, design method in wideband operational amplifier design optimization is proposed and the settling time and power consumption of operational amplifier can be effectively decreased In addition, an improved high speed dynamic comparator is used in this design Fabricated in a 1.8V 0.18μm CMOS process, this A/D converter with the proposed MDAC circuit achieves a signal to noise and distortion ratio (SNDR) of 54.6dB and an effective number of bits (ENOB) of 7.83bit with a 35MHz input signal at the 80MHz sample rate.

Key words: multiplying digital-to-analog converter, amplifier optimization, transmission gate, dynamic comparator, pipelined analog-to-digital converter

中图分类号:

TN431.2

董嗣万;朱樟明;刘敏杰;杨银堂. 用于8位80MS/s模数转换器的增益数模单元电路[J]. J4, 2016, 43(1): 162-166+172.

DONG Siwan;ZHU Zhangming;LIU Minjie;YANG Yintang. Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter[J]. J4, 2016, 43(1): 162-166+172.

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用于8位80MS/s模数转换器的增益数模单元电路

Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter

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