西安电子科技大学学报 ›› 2016, Vol. 43 ›› Issue (4): 23-28.doi: 10.3969/j.issn.1001-2400.2016.04.005

• 研究论文 • 上一篇    下一篇

一种双采样1.2V 7位125MS/s流水线ADC的设计

王晓飞;郝跃   

  1. (西安电子科技大学 宽带隙半导体国家重点学科实验室,陕西 西安  710071)
  • 收稿日期:2015-06-02 出版日期:2016-08-20 发布日期:2016-10-12
  • 作者简介:王晓飞(1979-),男,西安电子科技大学博士研究生,E-mail:xjtuwxf@126.com.
  • 基金资助:

    国家自然科学基金资助项目(61204085, 61334002)

Design of double sample 1.2V 7bit 125MS/s pipelined ADC

WANG Xiaofei;HAO Yue   

  1. (State Key Lab. of Wide Bandgap Semiconductor Technology Disciplines, Xidian Univ., Xi'an  710071, China)
  • Received:2015-06-02 Online:2016-08-20 Published:2016-10-12

摘要:

为了满足片上系统对模数转换器的低功耗和高性能的要求,设计并实现了一种1.2V 7位125MS/s双采样流水线模数转换器.该模数转换器采用了一种新的运算放大器共享技术以及相应的时序关系,从而消除了采样时序失配问题,并减小了整个模数转换器的功耗和面积.该模数转换器采用0.13μm CMOS工艺实现,测试结果表明,该模数转换器的最大信噪失真比为43.38dB,有效位数为6.8位.在电源电压为1.2V、采样速率为125MS/s时,该模数转换器的功耗仅为10.8mW.

关键词: 双采样, 运放共享, 时间交织, 流水线型模数转换器

Abstract:

A 7bit 125MS/s double sample pipelined ADC which can achieve a low power and a high performance for the SoC system is presented. The presented ADC with op-amp sharing between two channels and a new timing scheme can not only eliminate sampling timing skew, but also has a low power and a small area. Test results show that the ADC designed in a 0.13μm CMOS process achieves a maximum SNDR of 43.38dB, and that ENOB is 6.8bits. The ADC consumes 10.8mW at 125MS/s under a 1.2V supply voltage.

Key words: double sample, op-amp sharing, time-interleaved, pipelined analog to digital converter