超低时延免迭代CORDIC算法

doi:10.3969/j.issn.1001-2400.2017.04.028

摘要/Abstract

摘要：

针对流水线结构实现的坐标旋转数字计算机算法精度必须用迭代次数作保证，而较多的迭代次数会导致时延过大、硬件资源消耗过多等问题，通过综合运用角度二极化重编码、角度区间折叠、合并迭代和优化查找表等原理，提出一种能够免去迭代运算的坐标旋转数字计算机实现算法．仿真实验结果表明，跟其他实现算法相比，该坐标旋转数字计算机算法只需要两个时钟周期便能得到输出结果，在硬件消耗和输出精度上也有一定改善，更适合高速、实时的应用场合．

关键词: 坐标旋转数字计算机, 免迭代, 二极化重编码, 可编程逻辑门阵列, 数字信号处理

Abstract:

The pipeline structure Coordinate Rotation Digital Computer (CORDIC) algorithm improves its precision by increasing the stages of iterations, which leads to a large delay, excessive consumption of hardware and limits its applications.The omit-iteration CORDIC algorithm is proposed to solve this problem by using the methods of binary to bipolar recoding, folding angle domain, merging iteration and optimizing the lookup table. Simulation results show that this method needs only two clock cycles to get the output and also makes improvement on the hardware consumption and its precision, especially having privilege to the application on high speed and real-time occasions compared with other realization of the CORDIC algorithm.

Key words: coordinate rotation digital computer, omit-iteration, binary to bipolar recoding, field-programmable gate array, digital signal processing

姚亚峰;冯中秀;陈朝. 超低时延免迭代CORDIC算法[J]. 西安电子科技大学学报, 2017, 44(4): 162-166.

YAO Yafeng;FENG Zhongxiu;CHEN Zhao. Ultra-low latency and omit-iteration CORDIC algorithm[J]. Journal of Xidian University, 2017, 44(4): 162-166.

参考文献

［1］ SHUKLA R, RAY K C. Low Latency Hybrid CORDIC Algorithm［J］. IEEE Transactions on Computers, 2014, 63(12): 3066-3078.
［2］ PRASAD N, TRIPATHY M R, DAS A D, et al. Efficient VLSI Implementation of CORDIC Based Direct Digital Synthesizer［J］. Advances in Intelligent Systems and Computing, 2015, 308(1): 597-603.
［3］刘马良, 朱樟明, 郭旭龙, 等. 一种4路内插CORDIC的14位吉赫兹DDS IP核［J］. 西安电子科技大学学报, 2013, 40(6): 62-66.
LIU Maliang, ZHU Zhangming, GUO Xulong, et al. 4-channel-interpolated 14-bit High Speed CORDIC DDS IP Core［J］. Journal of Xidian University, 2013, 40(6): 62-66.
［4］ MUNOZ S D, HORMIGO J. High-throughput FPGA Implementation of QR Decomposition［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2015, 62(9): 861-865.
［5］ KHURSHID B, MIR R N, KUMAR A, et al. A Hybrid-radix Approach for Efficient Implementation of Unfolded CORDIC Architectures for FPGA Platforms ［C］//Proceedings of the 2014 International Conference on Signal Processing and Integrated Networks. Piscataway: IEEE , 2014: 453-457.
［6］ RAO P R, CHAKRABARTI I. High-performance Compensation Technique for the Radix-4 CORDIC Algorithm［J］. IEE Proceedings: Computers and Digital Techniques, 2002, 149(5): 219-228.
［7］ HU Y H, CHERN H H M. A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding(BAR)［J］. IEEE Transactions on Computers, 1996, 45(12): 1370-1378.
［8］徐成, 秦云川, 李肯立, 等. 免缩放因子双步旋转 CORDIC算法［J］. 电子学报, 2014, 42(7): 1441-1445.
XU Cheng, QIN Yunchuan, LI Kenli, et al. Double-step Scaling Free CORDIC［J］. Acta Electronica Sinica, 2014, 42(7): 1441-1445.
［9］ AGGARWAL S, MEHER P K, KHARE K. Concept, Design, and Implementation of Reconfigurable CORDIC［J］. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2016, 24(4): 1588-1592.
［10］张朝柱, 韩吉南, 燕慧智. 高速高精度固定角度旋转CORDIC算法的设计与实现［J］. 电子学报, 2016, 44(2): 485-490.
ZHANG Chaozhu, HAN Jinan, YAN Zhihui. Design and Implementation of CORDIC Algorithm for High Speed and Precision Fixed Angle of Rotation［J］. Acta Electronica Sinica, 2016, 44(2): 485-490.
［11］ MEHER P K, PARK S Y. CORDIC Designs for Fixed Angle of Rotation［J］. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2013, 21(2): 217-228.
［12］姚亚峰, 付东兵, 杨晓非. 基于CORDIC改进算法的高速DDS电路设计［J］. 华中科技大学学报: 自然科学版, 2009, 37(2): 25-27.
YAO Yafeng, FU Dongbing, YANG Xiaofei. Implement of High Speed DDS Circuit Design Using Improved CORDIC Algorithm［J］. Journal of Huazhong University of Science and Technogy: Natural Science Edition, 2009, 37(2): 25-27.
［13］ MADISETTI A, KWENTUS A Y, Jr WILLSON A N. A 100MHz, 16b, Direct Digital Frequency Synthesizer with a 100dBc Spurious Free Dynamic Range［J］. IEEE Journal of Solid-State Circuits, 1999, 34(8): 1034-1043.
［14］ JUANG T B, HSIAO S F, TSAI M Y. Para-CORDIC: Parallel CORDIC Rotation Algorithm［J］. IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2004, 51(8): 1515-1524.
［15］ KAMBO H M A D, KHAN S A. IS-CORDIC: a Fixed-point Inverse Recoded Single Iteration CORDIC Architecture［J］. International Journal of Electronics, 2014, 101(6): 789-807.

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[10]	朱哲勇;沈福民;陈伯孝. 基于DSP的步进频率雷达仿真信号源的研制[J]. J4, 1999, 26(6): 705-709.
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