西安电子科技大学学报

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3.3V CMOS工艺下5V电源轨的ESD箝位电路

陈迪平;董刚   

  1. (湖南大学 物理与微电子科学学院,湖南 长沙 410082)
  • 收稿日期:2017-09-28 出版日期:2018-10-20 发布日期:2018-09-25
  • 作者简介:陈迪平(1962-),男,教授,E-mail: chdp@hnu.edu.cn
  • 基金资助:

    国家自然科学基金资助项目(61474041)

ESD power-rail clamp circuit with a 5V power in the 3.3V CMOS process

CHEN Diping;DONG Gang   

  1. (College of Physics and Microelectronics Science, Hunan Univ., Changsha 410082, China)
  • Received:2017-09-28 Online:2018-10-20 Published:2018-09-25

摘要:

基于传统栅极接地NMOS静电放电电源箝位结构,针对5V供电情况,通过电平移位及低漏电流续流措施,实现了3.3V CMOS集成电路工艺条件下5V电源轨的新型静电放电箝位电路,避免了高压工艺造成的成本增加.该电路采用分级驱动及分级泄放措施,降低了正常工作时电源箝位电路的漏电流.采用中芯国际0.18μm CMOS集成电路工艺库模型,仿真验证了电路的正确性; 流片结果通过了人体模型±4000V测试,该电路可成功用于5V电源轨静电放电保护.

关键词: 静电放电, 保护电路, 分级驱动, 泄漏电流

Abstract:

Considering the 5V power supply, a novel ESD(electrostatic discharge) circuit with a 5V power rail based on a conventional GG-NMOS (Gate-Ground NMOS) ESD power-rail clamp circuit is designed by the method of level shifters and the low follow current in the 3.3V CMOS process to avoid a higher cost under the high-voltage process. Due to progressively driving and releasing steps of the optimized circuit, the leakage current is decreased in a regular operation. Moreover, the circuit is verified with simulations based on models in the SMIC's 0.18μm CMOS process technology library and the fabricated ESD power-rail clamp circuit has passed the HBM (Human Body Model) ESD test at ±4000V. The circuits can be successfully used for the 5V power rail ESD protection.

Key words: electro-static discharge, protection circuits, hierarchical driver, leakage current