西安电子科技大学学报 ›› 2018, Vol. 45 ›› Issue (6): 118-122.doi: 10.3969/j.issn.1001-2400.2018.06.020

• 研究论文 • 上一篇    下一篇

ESD应力下改进型SCR器件设计与漏电特性优化

刘湖云;梁海莲;顾晓峰;马艺珂;王鑫   

  1. (江南大学 物联网技术应用教育部工程研究中心,江苏 无锡 214122)
  • 收稿日期:2017-11-07 出版日期:2018-12-20 发布日期:2018-12-20
  • 作者简介:刘湖云(1994-),女,江南大学硕士研究生,E-mail:861485213@qq.com
  • 基金资助:
    国家自然科学基金资助项目(61504049);中国博士后基金资助项目(2016M600361);江苏省自然科学基金资助项目(BK20150156);江苏省研究生科研与实践创新计划资助项目(KYCX17_1487)

Design of modified SCR devices and optimization of the leakage characteristics under ESD stress

LIU Huyun;LIANG Hailian;GU Xiaofeng;MA Yike;WANG Xin   

  1. (Engineering Research Center of IoT Technology Applications (Ministry of Education), Jiangnan Univ., Wuxi 214122, China)
  • Received:2017-11-07 Online:2018-12-20 Published:2018-12-20

摘要: 为探讨片上集成电路静电放电防护的易闩锁与漏电软失效问题,设计了一种内嵌MOS结构的N跨桥可控硅器件.传输线脉冲测试结果表明:与传统N跨桥改进型可控硅相比,该器件的电压回滞幅度减小了约28.6%.然而,当作用于该器件的瞬态电流从2.0A增大到3.2A时,漏电流从2.8×10-7A逐渐退化至1.7×10-5A,器件较易发生软失效.借助TCAD技术,仿真结果表明:在10-4A的静电脉冲应力作用下,该器件内部晶格温度高达1160.5K.通过优化内嵌MOS结构的N跨桥可控硅器件的版图及其金属布线,削弱器件内部的功率密度聚集效应,可使器件在相同电应力下漏电流稳定在10-9A量级.因此,该版图优化方法可有效地抑制器件的局部过热,提高片上集成电路的静电放电防护方案的热稳定性.

关键词: 静电放电, 可控硅, 漏电特性, 版图优化, 热效应

Abstract: In order to investigate the easy latch-up and soft failure problem of on-chip integrated circuit electrostatic discharge (ESD) protection, a silicon controlled rectifier (SCR) embedded with the N-bridge and MOS (SCR-N-MOS) is proposed. The transmission line pulse test results show that the voltage snapback margin of the SCR-N-MOS is reduced by about 28.6% compared to the conventional N-bridge modified SCR. However, the leakage current of the SCR-N-MOS degrades gradually from 2.8×10-7A to 1.7×10-5A when the ESD transient current increases from 2.0A to 3.2A, resulting in soft failure. The technology computer aided design simulations of the SCR-N-MOS indicate that the lattice temperature increases  up to 1160.5K under an ESD current stress of 10-4A. By optimizing the layout of the SCR-N-MOS and the metal wiring, the power density crowding effect is weakened and the leakage current can be decreased and maintained in the order of 10-9A under the same stress. Therefore, the layout optimization method can effectively suppress the local overheating and improve the thermal stability of the on-chip integrated circuit ESD protection.

Key words: electrostatic discharge, silicon controlled rectifier, leakage characteristics, layout optimization, thermal effect

中图分类号: 

  • TN335