VLSI设计中互连耦合噪声的估计

VLSI设计中互连耦合噪声的估计

董刚;杨银堂;李跃进;柴常春

(西安电子科技大学微电子研究所,陕西西安 710071)

收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2005-04-20 发布日期:2005-04-20

Estimation of coupling noise in VLSI design

DONG Gang;YANG Yin-tang;LI Yue-jin;CHAI Chang-chun

(Research Inst. of Microelectronics, Xidian Univ., Xi'an 710071, China)

Received:1900-01-01 Revised:1900-01-01 Online:2005-04-20 Published:2005-04-20

摘要/Abstract

摘要： 随着互连尺寸及其间距的减小，由电容引起的耦合效应已成为影响VLSI设计的关键因素之一．采用耦合互连的L模型，基于主极点近似的方法给出了耦合噪声的时域解析表达式，讨论了影响峰值噪声电压的因素．与已有的方法相比，模型得到了简化，而精度并未损失，它可以广泛应用于考虑耦合效应的版图优化．

关键词: 互连耦合噪声, 主极点近似, 灵敏度

Abstract: The coupling effect induced by capacitance has become a key factor in VLSI design, as taller and narrower wires are now placed closer to each other. In this paper, we apply the L model for coupling interconnects and present an analytical expression for coupling noise based on dominant-pole approximation. The factors affecting peak noise are discussed. Compared with the methods available, the model is simplified without lowering accuracy. It can be used in noise-aware layout optimization.

Key words: interconnect coupling noise, dominant-pole approximation, sensitivity

中图分类号:

TN405.97

董刚;杨银堂;李跃进;柴常春. VLSI设计中互连耦合噪声的估计[J]. J4, 2005, 32(2): 276-279.

DONG Gang;YANG Yin-tang;LI Yue-jin;CHAI Chang-chun.

Estimation of coupling noise in VLSI design

[J]. J4, 2005, 32(2): 276-279.

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