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一种高效的H.264 CABAC解码器的VLSI结构


  1. 西安电子科技大学 综合业务网理论及关键技术国家重点实验室,陕西 西安 710071
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2006-12-20 发布日期:2006-12-20

An efficient VLSI architecture of the CABAC decoder in H.264

SHI Ying-bo;LI Yun-song;ZHANG Jian-long   

  1. State Key Lab. of Integrated Service Networks, Xidian Univ., Xi’an 710071, China
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-12-20 Published:2006-12-20


提出一种H.264/AVC中基于上下文的自适应二进制算术编码(CABAC)解码器的硬件设计方法,在采用并行结构的基础上,给出了一种高效的VLSI实现方案.采用两级有限状态机结构控制宏块解码过程,并通过对残差系数存储器的定时清零解决了数据存储耗时的问题,大大降低了解码控制的复杂度,从而提高解码速度,达到每1至2个时钟解出1比特.仿真结果表明,该方案能满足H.264/AVC main profile CIF 30fps实时解码的要求.

关键词: H.264/AVC, CABAC解码器, 大规模集成电路, 有限状态机


A hardware implementation of the Context-based Adaptive Binary Arithmetic Coding(CABAC) decoder for H.264/AVC is presented. Based on the full use of the parallel architecture, an efficient solution for VLSI implementation is described. By developing the two-level finite state machines to control the decoding process and adopting the memory clear schedule to solve the problem of coefficients storage being time-consuming, the complexity of CABAC-decoder implementation is reduced, and the speed is increased to generate one bit within one or two cycles. Simulation results testify that our design can meet the needs of decoding the H. 264/AVC main profile CIF bit stream at 30fps in real time.

Key words: H.264/AVC, CABAC-decoder, VLSI, finite state machine


  • TN919.81