J4 ›› 2009, Vol. 36 ›› Issue (3): 541-546.

• 研究论文 • 上一篇    下一篇



  1. (西安微电子技术研究所,陕西 西安  710075)
  • 收稿日期:2008-06-30 修回日期:2008-10-23 出版日期:2009-06-20 发布日期:2009-07-04
  • 通讯作者: 刘红侠
  • 基金资助:


Effective algorithm of parallel twiddle factor generation for programmable FFT processing and its implementation

LIU Hong-xia;YANG Liang;HUANG Jin;HUANG Shi-tan   

  1. (Xi'an Microelectronics Technology Institute, Xi'an  710075, China)
  • Received:2008-06-30 Revised:2008-10-23 Online:2009-06-20 Published:2009-07-04
  • Contact: LIU Hong-xia


为了解决FFT处理并行旋转因子产生复杂、所需存储资源多的问题,该文在分体存储器结构的基础上,提出了一种新的旋转因子存储、访问策略.该策略保证混合基4/2 FFT算法每个蝶式运算所需的3个旋转因子均可无冲突并行访问,且在同一个旋转因子查找表的基础上,使计算任意小于最大可处理长度的FFT时,各级访问旋转因子地址的产生仅与最大可处理长度有关,而与当前处理长度无关.该算法仅用一个可移位累加数寄存器,实现计算过程中旋转因子地址产生的级间切换,且使一个存储体容量及访问次数减少了一半以上.

关键词: 快速傅里叶变换(FFT), 旋转因子, 混合基4/2, 地址产生单元, FFT处理器


In order to resolve the problem of high complexity and high area consumption in designing a twiddle factor address generator that generates three addresses in every clock cycle, this paper presents a new storage and access strategy of twiddle factors based on the Multi-bank memory structure. The strategy guarantees that the three twiddle factors needed by a butterfly computation of mixed-radix 4/2 FFT algorithm can be accessed simultaneously without conflict. This twiddle factor generating algorithm based on one lookup table for an arbitrary size FFT is dependent only on its maximum size that can be processed. At the same time, the transition from one stage to another can be implemented with a shift addend register. Therefore, this algorithm can be implemented with less complexity and area consumption than any other existing design. In addition, the number of accesses to one of those banks and its size are reduced by at least 50 percent.

Key words: fast Fourier transform(FFT), twiddle factors, mixed radix-4/2, address generating unit, FFT processor


  • TP303