全数字接收机中一种低功耗插值滤波器结构及其VLSI实现

doi:10.3969/j.issn.1001-2400.2010.02.025

J4 ›› 2010, Vol. 37 ›› Issue (2): 320-325.doi: 10.3969/j.issn.1001-2400.2010.02.025

全数字接收机中一种低功耗插值滤波器结构及其VLSI实现

邓军^1,2;杨银堂²

(1. 西安电子科技大学电子工程学院，陕西西安 710071;
2. 西安电子科技大学微电子学院，陕西西安 710071)

收稿日期:2009-08-18 出版日期:2010-04-20 发布日期:2010-06-03
通讯作者: 邓军
作者简介:邓军(1976-)，男，高级工程师，西安电子科技大学博士研究生，E-mail: dengjunxd@163.com．
基金资助:
国家自然科学基金资助项目(60466047);陕西省科学技术研究发展计划资助项目(2009K08-30)

Structure of the low-power interpolation filter and its VLSI implementation for all-digital receiver

DENG Jun^1,2;YANG Yin-tang²

(1. School of Electronic Engineering, Xidian Univ., Xi'an 710071， China;
2. School of Microelectronic, Xidian Univ., Xi'an 710071， China)

Received:2009-08-18 Online:2010-04-20 Published:2010-06-03
Contact: DENG Jun

摘要/Abstract

摘要：

插值滤波器的设计是全数字接收机中码元同步算法的关键技术．本文主要探求一种适合于VLSI实现的插值滤波器结构，在拉格朗日立方插值滤波器的Farrow结构基础上，融入了流水线技术和并行处理技术以提高滤波器运算速率．对改进后的结构与原结构进行复杂度对比、运算速率对比和功耗对比，并在FPGA上实现．仿真与实现结果表明，该结构有着更快的运行速度、更低的功耗．

关键词: 全数字接收机, VLSI, 插值滤波器, Farrow结构

Abstract:

The interpolation filter is the key technology for realizing bit synchronization in all-digital receiver. This paper introduces the structure of the interpolation filter, which is suitable for VLSI. A new structure based on the Farrow structure of Lagrange is proposed, which can be used to improve the operational rate of the filter by pipelining and Parallel processing technology. A comparison in operational rate, hardware complexity and the energy consumption between improved structure and original structure is made. It has been realized by using FPGA.Simulation and experiment show that the structure has a faster operational rate and lower power.

Key words: all digital receiver, VLSI, interpolation filter, Farrow structure

邓军;杨银堂. 全数字接收机中一种低功耗插值滤波器结构及其VLSI实现[J]. J4, 2010, 37(2): 320-325.

DENG Jun. Structure of the low-power interpolation filter and its VLSI implementation for all-digital receiver[J]. J4, 2010, 37(2): 320-325.

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全数字接收机中一种低功耗插值滤波器结构及其VLSI实现

Structure of the low-power interpolation filter and its VLSI implementation for all-digital receiver

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