J4 ›› 2014, Vol. 41 ›› Issue (4): 36-40+192.doi: 10.3969/j.issn.1001-2400.2014.04.007

• 研究论文 • 上一篇    下一篇

一种新型分布式互连线功耗优化模型

张岩;杨银堂   

  1. (西安电子科技大学 宽禁带半导体材料与器件教育部重点实验室,陕西 西安  710071)
  • 收稿日期:2013-07-05 出版日期:2014-08-20 发布日期:2014-09-25
  • 通讯作者: 张岩
  • 作者简介:张岩(1982-),女,西安电子科技大学博士研究生,E-mail: zylap@aliyun.com.
  • 基金资助:

    国家自然科学基金资助项目(60606006);陕西省科技统筹创新工程计划资助项目(2011KTCQ01-19);国家部委预研基金资助项目(9140A23060111)

Novel distributed optimal interconnection power model

ZHANG Yan;YANG Yintang   

  1. (Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an  710071, China)
  • Received:2013-07-05 Online:2014-08-20 Published:2014-09-25
  • Contact: ZHANG Yan

摘要:

基于集总式互连线功耗模型,给出了一种分布式动态功耗表达式,在此基础上,采用非均匀互连线结构,提出了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连动态功耗优化模型.并在90nm和65nm CMOS工艺节点下,采用matlab软件验证了文中模型的有效性,在工艺约束下,同时不牺牲延时、带宽和面积时,所提模型能够降低30%左右的互连线功耗.该模型适用于大规模集成电路互连优化设计.

关键词: 集总式互连, 分布式互连, 功耗优化模型, 非均匀互连线

Abstract:

Based on the lumped interconnection power model, a distributed dynamic power model is presented first. Then by adopting a non-uniform interconnection structure, a novel optimal interconnection power model is proposed, which is constrained by delay, bandwidth, area, minimum interconnection width and minimum interconnection space. The validity of the proposed model is verified by 90nm and 65nm CMOS technology. The results indicate that the proposed model can reduce power consumption as high as 30%, with the delay, area, bandwidth not deteriorated. The proposed optimal model can be used for the interconnection optimal design in large scale integrated circuits.

Key words: lumped interconnect, distributed interconnect, optimal power model, non-uniform interconnection

中图分类号: 

  • TN402