一种面向卷积神经网络加速器的高性能乘累加器

doi:10.19665/j.issn1001-2400.2020.04.008

摘要/Abstract

摘要：

针对现有卷积神经网络加速器中的乘累加器普遍存在的面积大、功耗高、速度慢的问题,设计了一种基于传输门结构的全定制高性能乘累加器。提出了一种适用于乘累加器的新型累加数据压缩结构,减少了硬件开销;提出了一种新的并行加法器架构,在与Brent Kung加法器相同硬件开销的情况下,降低了门延迟级数,提高了计算速度;利用传输门的优点对乘累加器各单元电路进行优化设计。基于笔者方法设计的16乘8定点数高性能乘累加器在SMIC 130nm tt工艺角下关键路径延迟为1.173 ns,版图面积为9049.41 μm ²,800MHz下平均功耗为4.153 mW。对比传统的乘累加器,速度约提高了37.42%,面积约减小了47.87%,在同等条件下功耗约降低了56.77%。

关键词: 乘累加器, 传输门, 累加压缩, 卷积神经网络, 高性能

Abstract:

The multiply-accumulator (MAC) in existing convolutional neural network(CNN) accelerators generally have some problems, such as a large area, a high power consumption and a long critical path. Aiming at these problems, this paper presents a high-performance MAC based on transmission gates for CNN accelerators. This paper proposes a new data accumulation and compression structure suitable for the MAC, which reduces the hardware overhead. Moreover, we propose a new parallel adder architecture. Compared with the Brent Kung adder, the proposed adder reduces the number of gate delay stages and improves the calculation speed without causing an increase in hardware resources. In addition, we use the advantages of the transmission gate to optimize each unit circuit of the MAC. The 16-by-8 fixed-point high performance MAC based on the methods presented in this paper has a critical path delay of 1.173ns, a layout area of 9049.41μm2, and an average power consumption of 4.153mW at 800MHz under the SMIC 130nm tt corner. Compared with the traditional MAC, the speed is increased by 37.42%, the area is reduced by 47.84%, and the power consumption is reduced by56.77% under the same conditions.

Key words: multiply accumulator, transmission gate, accumulation and compression, convolutional neural network, high performance

中图分类号:

孔鑫,陈刚,龚国良,鲁华祥,毛文宇. 一种面向卷积神经网络加速器的高性能乘累加器[J]. 西安电子科技大学学报, 2020, 47(4): 55-63.

KONG Xin,CHEN Gang,GONG Guoliang,LU Huaxiang,Mao Wenyu. High performance multiply-accumulator for the convolutional neural networks accelerator[J]. Journal of Xidian University, 2020, 47(4): 55-63.

图/表 12

图1

图2

图3

图4

表1

改进型基4 Booth编码真值表"

$B 2 n + 1$	$B 2 n$	$B 2 n - 1$	operate	S_NEG	S_ONE	$S ONE ˉ$	S_ZERO
0	0	0	0	0	0	1	1
0	0	1	A	0	1	0	0
0	1	0	A	0	1	0	0
0	1	1	2A	0	0	1	0
1	0	0	-2A	1	0	1	0
1	0	1	-A	1	1	0	0
1	1	0	-A	1	1	0	0
1	1	1	0	1	0	1	1

表1

图5

图6

图7

图8

表2

表3

表4

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性能参数指标	参数值
工艺技术	SMIC 130nm PDK
版图尺寸/μm²	9049.41
输入位宽/bit	16×8
输出位宽/bit	32
供电电压/V	1.08~1.32
关键路径延迟/ns	1.173
时钟频率/MHz	800
平均功耗/mW	4.153

单元电路	实现方式	关键路径延迟/ns	版图面积/μm²	平均功率/μW,500MHz
改进型Booth编码器	传输门	0.199	18.696	0.839
	标准单元库	0.253	32.275	7.417
	MBE-III^[16]	0.210	40.344	9.220
改进型Booth译码器	传输门	0.294	16.467	0.643
	标准单元库	0.454	32.275	6.834
	MBE-III	0.521	46.215	8.711
CSA单元电路 (全加器)	传输门	0.275	22.47	3.237
CSA单元电路 (全加器)	标准单元库	0.407	40.34	11.287
4-2压缩器	传输门	0.421	46.71	6.415
4-2压缩器	标准单元库	0.655	80.69	21.370
所提出的加法器所提出的加法器	传输门	1.197	1688.54	260.699
所提出的加法器所提出的加法器	标准单元库	1.447	1958.03	583.174
Brent Kung加法器	标准单元库	1.493	1986.75	638.767
超前进位加法器	标准单元库	1.486	1933.62	596.283
Kogge Stone加法器	标准单元库	1.237	3738.54	1131.161

名称	工艺库	实现方式	关键路径延迟/ns	版图面积/μm²	功耗/mW,400MHz
所提出乘累加器	SMIC 130nm PDK	全定制设计方法	1.633	9049.41	1.988
所提出乘累加器	SCC013UGHDLVT	数字后端设计	1.880	15486.07	3.849
传统乘累加器	SCC013UGHDLVT	数字后端设计	2.244	17358.74	4.599
文献[5]中累加器	SCC013UGHDLVT	数字后端设计	2.347	17077.85	4.897
文献[6]中累加器	SCC013UGHDLVT	数字后端设计	1.894	16518.43	3.878
文献[7]中累加器	SCC013UGHDLVT	数字后端设计	1.944	16273.13	4.329