关键词: 低噪声, 高速, 电荷泵, 锁相环

Abstract:

A high-performance Charge Pump Phase Lock Loop(CPPLL) of low-noise high-speed is presented. The all-differential structure is used in design; Two kinds of high-speed low-power consumption logic circuits—CMOS and Current Mode Logic(CML) are introduced to compose the operation unit; the proposed differential charg-pump loop-filter saves the die area observably. The entire circuit is implemented in the 0.6 μm BiCMOS process. Results from HSPICE simulation show that the power dissipation is  77 mW, that the center-frequency is 223 MHz, and that the frequency range is 102 MHz~800 MHz. The specifications are satisfied and the characteristics such as noise, speed, and power consumption are optimized remarkably.

Key words: low noise, high speed, charge pump, PLL