采用EMS算法的多元LDPC译码器的FPGA实现

doi:10.3969/j.issn.1001-2400.2011.05.005

J4 ›› 2011, Vol. 38 ›› Issue (5): 27-33.doi: 10.3969/j.issn.1001-2400.2011.05.005

采用EMS算法的多元LDPC译码器的FPGA实现

何光华;白宝明;李博;林伟

(西安电子科技大学综合业务网理论及关键技术国家重点实验室，陕西西安 710071)

收稿日期:2010-07-12 出版日期:2011-10-20 发布日期:2012-01-14
通讯作者: 何光华
作者简介:何光华(1984-)，男，西安电子科技大学博士研究生，E-mail: ghhe@mail.xidian.edu.cn
基金资助:
国家自然科学基金资助项目(60972046,61001130);长江学者和创新团队发展计划资助项目(IRT0852);国家科技重大专项课题资助项目(2009zx03003-011, 2010zx03003-003-03)

FPGA implementation of a non-binary LDPC decoder using the EMS algorithm

HE Guanghua;BAI Baoming;LI Bo;LIN Wei

(State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an 710071， China)

Received:2010-07-12 Online:2011-10-20 Published:2012-01-14
Contact: HE Guanghua

摘要/Abstract

摘要：

针对多元低密度奇偶校验码(LDPC)译码器的资源消耗过大问题，设计了一种采用扩展最小和算法的低资源需求的多元LDPC译码器．采用以块为单位对信息进行迭代更新和Flooding传递调度策略的结构．为降低译码器的存储资源和逻辑资源，首先减小传递信息的深度，将变量节点更新和校验节点更新进行联合设计．同时，利用迭代时间差对变量节点更新和校验节点信息所需的资源进行复用．在具体实现中，对一个GF(64)域上码长为1044bit的非规则多元LDPC码，采用Xilinx公司XC4VLX60的现场可编程逻辑门阵列(FPGA)芯片设计了译码器．与现有文献相比，所提出的译码器结构可节约54%的存储资源和逻辑资源，且提高了译码速度和吞吐量．

关键词: 多元LDPC码, 有限域, FPGA, 译码器

Abstract:

Due to the high resources demand during the decoding process of non-binary LDPC codes, a non-binary LDPC decoder based on the EMS (Extended Min-Sum) algorithm is proposed. The messages are updated iteratively in the block unit, and the flooding schedule is utilized in this proposed decoder. To reduce the storage resources and logical resources, the messages are first contracted in length. Then, the resources are multiplexed between the process of check nodes updating and that of variable nodes updating by the time difference. An FPGA chip for decoding an irregular non-binary LDPC over GF(64) of length 1044bit has been developed based on the Xilinx XC4VLX60 FPGA device. Compared to the existing solutions, about 54% storage resources and logical resources can be saved. Meanwhile, the decoding speed and throughput can be greatly improved.

Key words: non-binary LDPC codes, Galois fields, FPGA, decoder

中图分类号:

TN911.21

何光华;白宝明;李博;林伟. 采用EMS算法的多元LDPC译码器的FPGA实现[J]. J4, 2011, 38(5): 27-33.

HE Guanghua;BAI Baoming;LI Bo;LIN Wei. FPGA implementation of a non-binary LDPC decoder using the EMS algorithm[J]. J4, 2011, 38(5): 27-33.

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采用EMS算法的多元LDPC译码器的FPGA实现

FPGA implementation of a non-binary LDPC decoder using the EMS algorithm

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