J4 ›› 2013, Vol. 40 ›› Issue (3): 115-120.doi: 10.3969/j.issn.1001-2400.2013.03.017

• 研究论文 • 上一篇    下一篇

一种高速低功耗的NoC时钟网络设计

刘毅1,2;陈博1;杨银堂1,2;刘刚1
  

  1. (1. 西安电子科技大学 微电子学院,陕西 西安  710071;
    2. 西安电子科技大学 宽禁带半导体材料与器件教育部重点实验室,陕西 西安  710071)
  • 收稿日期:2011-12-22 出版日期:2013-06-20 发布日期:2013-07-29
  • 作者简介:刘毅(1971-),男,副教授,博士,E-mail: yiliu@mail.xidian.edu.cn.
  • 基金资助:

    国家自然科学基金资助项目(61172030);中央高校基本科研业务费专项资金资助项目(K50510250004)

High-speed low-power clock network design for NoC

LIU Yi1,2;CHEN Bo1;YANG Yintang1,2;LIU Gang1,2   

  1. (1. School of Microelectronic, Xidian Univ., Xi'an  710071, China;
    2. Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an  710071, China)
  • Received:2011-12-22 Online:2013-06-20 Published:2013-07-29

摘要:

为了实现高速低功耗的片上网络时钟网络,针对MESH型片上网络,用金属-绝缘质-金属电容替代MOS电容作为发送端驱动电容和接收端耦合电容,设计了一种基于改进的电容驱动型低摆幅收发器的瀑布型时钟网络.Spectre仿真结果表明,在0.13μm CMOS工艺条件下,该时钟网络的时钟频率可达5GHz,功耗和延时仅为传统时钟网络的49%和55%,并具有更好的噪声抑制能力.

关键词: 片上网络, 时钟网络, 低功耗, 低摆幅

Abstract:

In order to achieve a high-speed low-power NoC(Network-on-chip) clock network, considering the Mesh NoC, a waterfall clock network based on the capacitively-driven low-swing transceiver in which we replace traditional MOS capacitance by metal-insulator-metal(MIM) capacitance as the driven capacitance and receiver coupling capacitance is proposed. These structures are simulated by 0.13μm CMOS technology with Spectre simulators. Results show that the proposed clock network can reach a high frequency up to 5GHz,compared with traditional networks, and this network allows up to 49% power saving and 55% delay reduction. At the same time, this network has a better noise suppression ability.

Key words: network-on-chip, clock network, low-power, low-swing

中图分类号: 

  • TN402