一种具有延迟校准功能的可编程多相位时钟电路

doi:10.3969/j.issn.1001-2400.2014.06.010

J4 ›› 2014, Vol. 41 ›› Issue (6): 57-64.doi: 10.3969/j.issn.1001-2400.2014.06.010

一种具有延迟校准功能的可编程多相位时钟电路

刘术彬¹;朱樟明¹;赵扬¹;恩云飞²;刘帘曦¹;杨银堂¹

(1. 西安电子科技大学微电子学院，陕西西安 710071；
2. 电子元器件可靠性物理及其应用技术重点实验室，广东广州 510610)

收稿日期:2013-10-06 出版日期:2014-12-20 发布日期:2015-01-19
作者简介:刘术彬(1983-)，男，西安电子科技大学博士研究生，E-mail: shuvin101@126.com．
基金资助:
国家自然科学基金资助项目(61234002，61322405，61306044，61376033)；国家863计划资助项目(2012AA012302，2013AA014103)；教育部博士点基金资助项目(20120203110017)；电子元器件可靠性物理及其应用技术重点实验室开放基金资助项目(ZHD201101)

Programmable mlti-phase clock circuit with delay calibration

LIU Shubin¹;ZHU Zhangming¹;ZHAO Yang¹;EN Yunfei²;LIU Lianxi¹;YANG Yintang¹

(1. School of Microelectronic, Xidian Univ., Xi'an 710071, China;
2. Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory, Guang Zhou 510610, China)

Received:2013-10-06 Online:2014-12-20 Published:2015-01-19

摘要/Abstract

摘要：

基于延迟锁相环原理，提出了一种新型的具有延迟校准功能的可编程多相位时钟电路，能为工作在80MHz的电荷耦合器件信号处理器提供精度高达390ps的时序信号．将主时钟的单周期等分为32份，通过可编程相位组合电路，产生相位及占空比可调的信号，能满足不同电荷耦合器件所需的最优工作时序．传统的延迟锁相环结构随着延迟单元的增加，延迟单元之间不匹配愈加明显，导致输出相位偏离理想位置．引入延迟校准电路可以显著降低相位之间的误差，校准后的多相位时钟信号接入可编程相位组合器进行选择组合，产生所需的高精度时序信号．基于SMIC 0.18μm 3.3V CMOS工艺完成设计，在80MHz主时钟下的后仿真结果表明：电路可产生占空比范围为2％～98％的输出时钟，校准后的延迟误差小于5ps，边到边抖动为 1.14ps，有效地保证了相位精度．

关键词: 电荷耦合器件, 延迟锁相环, 延迟校准环路, 可编程相位组合器

Abstract:

Based on the principle of the delay-locked loop (DLL), this paper introduces a programmable multi-phase clock circuit with a delay calibration loop. The proposed circuit offers a clock signal with a precision of 390ps and optimum timing for a variety of CCD signal processors. One cycle of the main clock is divided into 32 parts equally, while timing with a tunable duty cycle is generated by the programmable phase combiner. The increase in delay elements worsens the delay time error between different phases of the output signals, and hence a delay time calibration loop is applied to suppress this effect. In SMIC 0.18μm 3.3V CMOS process, with a 80MHz main clock, the post simulation results show that the proposed circuit generates an output clock with a 2％～98％ duty cycle, a 1.14ps edge to edge jitter and a less than 5ps calibrated delay time error.

Key words: charge couple device, delay locked loop, delay calibration loop, programmable phase combiner

刘术彬;朱樟明;赵扬;恩云飞;刘帘曦;杨银堂. 一种具有延迟校准功能的可编程多相位时钟电路[J]. J4, 2014, 41(6): 57-64.

LIU Shubin;ZHU Zhangming;ZHAO Yang;EN Yunfei;LIU Lianxi;YANG Yintang. Programmable mlti-phase clock circuit with delay calibration[J]. J4, 2014, 41(6): 57-64.

参考文献

［1］ Yang Zuoting, Wang Hongwei, Qiao Weidong, et al. The Research of Space Telescope CCD Camera Image Resource Simulative System ［C］//International Conference on Electronics and Optoelectronics. Piscataway: IEEE Computer Society, 2011: 386-389.
［2］刘鸿雁, 栾孝丰, 刘传军. 低噪声高速全差分BiCMOS电荷泵锁相环设计［J］. 西安电子科技大学学报, 2009, 36(3): 441-446.
Liu Hongyan, Luan Xiaofeng, Liu Chuanjun. Design of the Low-noise High-speed Differential Charge-pump Phase-look Loop ［J］. Journal of Xidian University, 2009, 36(3): 441-446.
［3］ Best R E. Phase-locked Loops: Theory, Design and Applications ［M］. New York: McGraw-Hill, 1998.
［4］ Shi F, Wu X, Yan Z. Improved Analytical Delay Models for RC-coupled Interconnects［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(7): 1639-1644.
［5］ Shinagawa M, Akazawa Y, Wakimoto T. Jitter Analysis of High-speed Sampling Systems［J］. IEEE Journal of Solid-state Circuits, 1990, 25(1): 220-224.
［6］ Lin Weiming, Teng Kuangfu, Liu ShenIuan. A Delay-locked Loop with Digital Background Calibration ［C］//IEEE Asian Solid-state Circuits Conference. Piscataway: IEEE, 2009: 317-320.
［7］ Deng Wei, Siriburanon M A, Miyahara T, et al. A 0.022mm2 970μW Dual-loop Injection-locked PLL with -243dB FOM Using Synthesizable All-digital PVT Calibration Circuits ［C］//IEEE International Solid-state Circuits Conference Digest of Technical Papers. Piscataway: IEEE, 2013: 248-249.
［8］ Hafez A A, Yang C K K. A Multi-phase Multi-frequency Clock Generator Using Superharmonic Injection Locked Multipath Ring Oscillators as Frequency Dividers［C］//IEEE Asian Solid State Circuits Conference. Piscataway: IEEE, 2012: 289-292.
［9］ Tan A H Y, Wei G Y. Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-phase Clock Generator［C］//IEEE Custom Integrated Circuits Conference. Piscataway: IEEE, 2006: 417-420.
［10］ Herzel F, Razavi B. A Study of Oscillator Jitter Due to Supply and Substrate Noise［J］. IEEE Transactions on Circuits and Systems, 1999, 46(1): 56-62.

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一种具有延迟校准功能的可编程多相位时钟电路

Programmable mlti-phase clock circuit with delay calibration

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