西安电子科技大学学报

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用于FPGA IP保护的低成本高性能PUF设计

张国栋;刘强;张齐军   

  1. (天津大学 电子信息工程学院,天津 300072)
  • 收稿日期:2015-09-21 出版日期:2016-12-20 发布日期:2017-01-19
  • 作者简介:张国栋(1989-),男,天津大学硕士研究生,E-mail:timgd_zhang@tju.edu.cn.
  • 基金资助:

    国家自然科学基金资助项目(61204022)

Low cost and high performance RO-PUF design for IP protection of FPGA implementations

ZHANG Guodong;LIU Qiang;ZHANG Qijun   

  1. (College of Electronic and Information Engineering, Tianjin Univ., Tianjin 300072, China)
  • Received:2015-09-21 Online:2016-12-20 Published:2017-01-19

摘要:

随着现场可编程门阵列在电子系统设计中的广泛应用,人们越来越重视基于现场可编程门阵列的知识产权保护问题.但在实际应用中,在现场可编程门阵列上实现环形振荡器型物理不可克隆函数还面临着诸多挑战,如环形振荡器型物理不可克隆函数电路的面积消耗很大; 有限的逻辑资源使得激励响应对数量有限,限制了该知识产权保护方法的应用范围.为了解决这些问题,首先提出了一种逻辑混合技术.该技术把物理不可克隆函数逻辑和正常电路逻辑在现场可编程门阵列实现中混合起来,以减少物理不可克隆函数的电路面积消耗.其次,采用了一种后处理方法,极大地增加了所设计环形振荡器型物理不可克隆函数的激励响应对数量.实验结果显示,文中设计的物理不可克隆函数的性能优异,可靠性、随机性和独特性分别为99.97%、50.37%、49.83%.同时,消耗的硬件资源比其他同等性能的物理不可克隆函数少了45%.

关键词: 物理不可克隆函数, 环形振荡器, 逻辑混合, 现场可编程阵列

Abstract:

As FPGAs have been adopted in many electronic system designs, intellectual property (IP) protection of FPGA implementations has become one of the major concerns in industry. The ring oscillator-based physical unclonable function (RO-PUF) has been investigated for IP authentication of FPGA implementations. However, integrating RO-PUF into FPGA implementations for practical applications still faces challenges: (1) it always introduces considerable hardware overheads; and (2) the limited set of challenge-response pairs (CRPs) due to limited circuit resources may not authenticate a large population of FPGA implementations with a small error. To address these issues, this paper first proposes an effective technique, logic fusion. It combines the RO logic of the PUF with the normal circuit logic, without increasing logic resource usage in FPGAs. Second, a post-processing procedure is exploited to expand the set of CRPs from the designed RO-PUF. Experimental results show that the reliability, randomness and uniqueness metrics of the designed RO-PUF are 99.97%, 50.37% and 49.83%, respectively. Compared with the existing RO-PUF design techniques, the area overhead can be reduced by 45% with the same performance.

Key words: physical unclonable function, ring oscillator, logic fusion, FPGA