低功耗时间交织12位500MS/s电荷域ADC

doi:10.3969/j.issn.1001-2400.2017.06.020

西安电子科技大学学报

低功耗时间交织12位500MS/s电荷域ADC

陈珍海1,4;魏敬和1;苏小波1,2;邹家轩1,2;张鸿3;于宗光1,2

(1. 中国电子科技集团第五十八研究所，江苏无锡 214035；
2. 西安电子科技大学微电子学院，陕西西安 710071;
3. 西安交通大学电信学院，陕西西安 710049;
4. 黄山学院信息工程学院，安徽黄山 245041)

收稿日期:2016-11-13 出版日期:2017-12-20 发布日期:2018-01-18
作者简介:陈珍海(1982-)，男，博士，E-mail: diaoyuds@126.com
基金资助:
国家自然科学基金资助项目(61474092, 61704161)；安徽高校自然科学研究重点资助项目(KJ2017A396)

Low power time-interleaved 12-bit 500MS／s charge-domain ADC

CHEN Zhenhai1,4;WEI Jinghe1;SU Xiaobo1,2;ZOU Jiaxuan1,2;ZHANG Hong3;YU Zongguang1,2

（1. No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China;
2. School of Microelectronics, Xidian Univ., Xi'an 710071, China;
3. School of Electronics and Information Engineering, Xi'an Jiaotong Univ., Xi'an 710049, China;
4. School of Information Engineering, Huangshan Univ., Huangshan 245041, China)

Received:2016-11-13 Online:2017-12-20 Published:2018-01-18

摘要/Abstract

摘要：

针对外部输入共模电荷变化及失调误差对高速电荷域流水线模数转换器精度产生限制的问题，提出了一种输入共模电荷前馈补偿电路和一种失调误差数模混合前台校准技术，可对输入共模电荷变化产生的共模电荷误差量和失调误差进行补偿．基于所提出的输入共模电荷前馈补偿电路和失调误差前台校准技术，在1P6M 018μm CMOS工艺条件下设计了一款12bit、500MS／s时间交织电荷域流水线模数转换器．测试结果表明，该模数转换器样片在全速采样时对于19.9MHz正弦输入信号转换得到的无杂散动态范围为77.5dB，信噪失真比为62.7dBFS; 并且输入共模电压在12V内变化时模数转换器的信噪比波动小于3dB，而功耗为220mW，有源芯片面积为624mm²．

关键词: 流水线模数转换器, 电荷域, 时间交织, 前馈补偿, 失调校准

Abstract:

A feed-forward common-mode(CM) charge compensation circuit and a foreground calibration technique for the high speed charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented to solve the problem that the precision of CD pipelined ADCs is restricted by the variation of the input CM charge and the offset error. The proposed compensation circuit and the calibration technique can compensate the CM charge and errors caused by the variation of the input CM charge and offset respectively. Based on the feed-forward CM charge compensation circuit and the offset error foreground calibration technique, a 12bit 500MS／s time-interleaved CD pipelined ADC is designed and realized in a 1P6M 018μm CMOS process. The ADC achieves the spurious free dynamic range (SFDR) of 775dB and the signal-to-noise-and-distortion ratio (SNDR) of 627dBFS for a 199MHz input at a full sampling rate. The variation of signal-to-noise ratio is less than 3dB for the input CM voltage in the 0 to 12V range. The power consumption of the prototype ADC is only 220mW at 18V supply and occupies the active die area of 624mm².

Key words: pipelined analog-to-digital converter, charge domain, time-interleaved, feed-forward compensation, offset calibration

陈珍海;魏敬和;苏小波;邹家轩;张鸿;于宗光. 低功耗时间交织12位500MS/s电荷域ADC[J]. 西安电子科技大学学报, 2017, 44(6): 109-115+137.

CHEN Zhenhai;WEI Jinghe;SU Xiaobo;ZOU Jiaxuan;ZHANG Hong;YU Zongguang. Low power time-interleaved 12-bit 500MS／s charge-domain ADC[J]. Journal of Xidian University, 2017, 44(6): 109-115+137.

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低功耗时间交织12位500MS/s电荷域ADC

Low power time-interleaved 12-bit 500MS／s charge-domain ADC

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