一种高速高宽带主从式采样保持电路

doi:10.3969/j.issn.1001-2400.2018.04.022

摘要/Abstract

摘要：

基于0.13μm SiGe BiCMOS工艺设计并实现了一种新型高速高宽带主从式采样保持电路．该电路采用PMOS源极跟随器作输入级实现了直流耦合，使得低频、低偏置电压信号也可以被正常采样．采用Cherry-Hooper放大器将带宽提升至18GHz．通过主从式采样结构和交叉耦合电容消除了信号馈通，使用互补三极管抵消了时钟馈通的影响，将无杂散动态范围控制在33～38dB．对比结果表明，这种设计方案在带宽方面具有较大的优势，并且具有较高的采样率．

关键词: 高速高宽带, 主从式采样, 采样保持电路, 信号馈通, 时钟馈通, 模数转换器

Abstract:

This paper presents a new-style high-speed broadband master-slave sampling and hold circuit based on the 0.13μm SiGe BiCMOS. In order to realize DC coupling and sample the low-frequency low-offset-voltage signal, the PMOS source follower is used in the input stage. The Cherry-Hooper structure is used to expand the bandwidth up to 18GHz. Signal feedthrough is cancelled by the master-slave sampling structure and cross-coupled capacitors. Clock feedthrough is attenuated by complementary bipolar transistors. The spurious free dynamic range is 33～38dB. Comparison results show that the proposed circuit has a big advantage in bandwidth and is able to sample at a high sampling rate.

Key words: high-speed and high-broadband, master-slave sampling structure, sample-and-hold circuit, signal feedthrough, clock feedthrough, analog-to-digital converter

丁浩;王建业;刘伟;熊永忠. 一种高速高宽带主从式采样保持电路[J]. 西安电子科技大学学报, 2018, 45(4): 123-128.

DING Hao;WANG Jianye;LIU Wei;XIONG Yongzhong. High-speed high-broadband master-slave sampling and hold circuit[J]. Journal of Xidian University, 2018, 45(4): 123-128.

参考文献

［1］ CASCELLA D, AVITABILE G, CANNONE F, et al. A 2-GS/s 0.35μm SiGe Track-and-hold Amplifier with 7-GHz Analog Bandwidth Using a Novel Input Buffer［C］//Proceedings of the 2011 IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2011: 113-116.
［2］王晓飞,郝跃. 一种双采样1.2V 7位125MS/s流水线ADC的设计［J］. 西安电子科技大学学报, 2016, 43(4): 23-28.
WANG Xiaofei, HAO Yue. Design of Double Sample 1.2V 7bit 125MS/s Pipelined ADC［J］. Journal of Xidian University, 2016, 43(4): 23-28.
［3］ SALAMA C A T. A Bipolar 2-G Sample/s Track-and-hold Amplifier(THA) in 0.35μm SiGe Technology［C］//Proceedings of the 2002 IEEE International Symposium on Circuits and Systems. Piscataway: IEEE, 2002: 573-576.
［4］ MADSEN K N, GATHMAN T D, DANESHGAR S, et al. A High-linearity, 30GS/s Track-and-hold Amplifier and Time Interleaved Sample-and-hold in an InP-on-CMOS Process［J］. IEEE Journal of Solid-State Circuits, 2015, 50(11): 2692-2702.
［5］ TRETTER G, FRITSCHE D, KHAFAJI M M, et al. A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS［J］. IEEE Transactions on Circuits Systems Ⅱ: Express Briefs, 2016, 63(3): 229-233.
［6］ HOLDENRIED C D, HASLETT J W, LYNCH M W. Analysis and Design of HBT Cherry-Hooper Amplifier with Emitter-follower Feedback for Optical Communications［J］. IEEE Journal of Solid-State Circuits, 2004, 39(11): 1959-1967.
［7］ JENSEN J C, LARSON L E. A Broadband 10-GHz Track-and-hold in Si/SiGe HBT Technology［J］. IEEE Journal of Solid-State Circuits, 2001, 36(3): 325-330.
［8］ JARA M, ALESSANDRI C, ABUSLEME A. Time-domain 1/f Noise Analysis of a Charge-redistribution Track-and-hold Circuit［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2018, 65(2): 161-165.
［9］ LIN Y A, YEH Y C, LIU Y C, et al. A 55-dB SFDR 16-GS/s Track-and-hold Amplifier in 0.18μm SiGe Using Differential Feedthrough Cancellation Technique［C］//Proceedings of the 2016 IEEE MTT-S International Microwave Symposium. Piscataway: IEEE, 2016: 1-4.
［10］ YANG Y J, CHEN C, XU W J, et al. A High Input Analog Bandwidth Track and Hold Circuit in HBT Technology［C］//Proceedings of the 2016 International NanoElectronics Conference. Piscataway: IEEE, 2016: 7589268.
［11］ LIN Y A, YEH Y C, CHANG H Y. A 27-GHz 45-dB SFDR Track-and-hold Amplifier Using Modified Darlington Amplifier and Cascoded SEF in 0.18-μm SiGe Process［C］//Proceedings of the 2017 IEEE MTT-S International Microwave Symposium. Piscataway: IEEE, 2017: 137-140.
［12］杨银堂,袁俊,张钊锋. 256MHz采样71dB动态范围连续时间ΣΔADC设计［J］. 西安电子科技大学学报, 2015, 42(1): 10-15.
YANG Yintang, YUAN Jun, ZHANg Zhaofeng. Continuous Time ΣΔ ADC Design with 256MHz Sampling and 71dB DR［J］. Journal of Xidian University, 2015, 42(1): 10-15.

[1]	于健海,尹亮. 用于微机械加速度计的亚微米工艺ADC设计[J]. 西安电子科技大学学报, 2019, 46(3): 140-147.
[2]	陈珍海, 魏敬和, 于宗光, 苏小波, 薛颜, 张鸿. 高精度电荷域ADC共模电荷误差前台校准电路[J]. 西安电子科技大学学报, 2018, 45(6): 137-143+149.
[3]	张章;余文成;解光军. 10bit 100MS/s混合型模数转换器[J]. 西安电子科技大学学报, 2018, 45(3): 80-85+116.
[4]	陈珍海;魏敬和;苏小波;邹家轩;张鸿;于宗光. 低功耗时间交织12位500MS/s电荷域ADC[J]. 西安电子科技大学学报, 2017, 44(6): 109-115+137.
[5]	陈珍海;于宗光;李现坤;魏敬和;黄嵩人;苏小波. 用于16bit 100MS/s ADC的高精度参考电压产生电路[J]. 西安电子科技大学学报, 2017, 44(3): 127-132+180.
[6]	黄嵩人;陈珍海;张鸿;李雪;钱宏文;于宗光. 用于电荷域流水线ADC的1.5位子级电路[J]. 西安电子科技大学学报, 2016, 43(6): 170-175.
[7]	王晓飞;郝跃. 一种双采样1.2V 7位125MS/s流水线ADC的设计[J]. 西安电子科技大学学报, 2016, 43(4): 23-28.
[8]	董嗣万;朱樟明;刘敏杰;杨银堂. 用于8位80MS/s模数转换器的增益数模单元电路[J]. J4, 2016, 43(1): 162-166+172.
[9]	曹超;马瑞;朱樟明;梁宇华;叶谦. 高精度SAR ADC非理想因素分析及校准方法[J]. J4, 2015, 42(6): 61-65+87.
[10]	杨银堂;袁俊;张钊锋. 256MHz采样71dB动态范围连续时间ΣΔADC设计[J]. J4, 2015, 42(1): 10-15.
[11]	佟星元;杨银堂;朱樟明;刘帘曦. 逐次逼近ADC无源器件的匹配性与高层次模型[J]. J4, 2011, 38(6): 123-129.
[12]	杨银堂;李迪;石立春. 一种用于14位1.28MS/sΣΔADC的数字抽取滤波器设计[J]. J4, 2010, 37(2): 315-319.