西安电子科技大学学报 ›› 2018, Vol. 45 ›› Issue (6): 137-143+149.doi: 10.3969/j.issn.1001-2400.2018.06.023

• 研究论文 • 上一篇    下一篇

高精度电荷域ADC共模电荷误差前台校准电路

陈珍海1,2;魏敬和2;于宗光2,3;苏小波2,3;薛颜2;张鸿4   

  1. (1. 黄山学院 信息工程学院,安徽 黄山 245041;
    2. 中国电子科技集团第五十八研究所,江苏 无锡 214035;
    3. 西安电子科技大学 微电子学院,陕西 西安 710071;
    4. 西安交通大学 微电子学院, 陕西 西安 710049)
  • 收稿日期:2017-12-18 出版日期:2018-12-20 发布日期:2018-12-20
  • 作者简介:陈珍海(1982-),男,博士,E-mail: diaoyuds@126.com
  • 基金资助:
    国家自然科学基金资助项目(61704161);安徽高校自然科学研究重点资助项目(KJ2017A396)

High precision common mode charge error fore-ground calibration circuit for the charge-domain ADC

CHEN Zhenhai1,2;WEI Jinghe2;YU Zongguang2,3;SU Xiaobo2,3;XUE Yan2;ZHANG Hong4   

  1. (1. School of Information Engineering, Huangshan Univ., Huangshan 245041, China; 
    2. No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China; 
    3. School of Microelectronics, Xidian Univ., Xi'an 710071, China; 
    4.School of Microelectronic, Xi'an Jiaotong Univ., Xi'an 710049, China)
  • Received:2017-12-18 Online:2018-12-20 Published:2018-12-20

摘要: 提出了一种数模混合型高精度共模电荷误差校准电路,可对电荷域流水线模数转换器中由增强型电荷传输电路电荷传输关断电压随工艺、电压和温度波动、输入共模电荷变化、各流水线子级中电容非线性而引起的各类共模电荷误差进行精确补偿.所提出的高精度共模电荷误差校准电路被运用于一款14bit210MS/s电荷域模数转换器中,并在1P6M 0.18μm CMOS工艺下实现.测试结果显示,该14bit模数转换器电路在210MS/s条件下对于30.1MHz单音正弦输入信号得到的无杂散动态范围为85.4dBc,信噪比为71.5dBFS,而模数转换器内核功耗仅为205mW,面积为3.15mm2

关键词: 流水线模数转换器, 电荷域, 前台校准, 低功耗, 共模电荷

Abstract: A mix-signal high precision common mode charge error calibration circuit is proposed. The calibration circuit can be used to compensate the common mode charge errors caused by the deviation of the charge transfer cutoff voltage of boosted charge transfer introduced by PVT variation, the variation of input common mode charge and the capacitor mismatch in the pipelined sub-stage circuit in the charge domain pipelined ADCs. Based on the proposed calibration circuit, a 14bit 210MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. Test results show that the 14bit 210MS/s ADC achieves the signal-to-noise ratio of 71.5dBFS and the spurious free dynamic range of 85.4dB, with 30.1MHz input single tone signal at 210MS/s, while the ADC core consumes the power of 205mW and occupies an area of  3.2mm2.

Key words: pipelined analog-to-digital converter, charge-domain, fore-ground calibration, low power, common-mode charge

中图分类号: 

  • TN432