一种采用互连线电容耦合的线计算电路设计

doi:10.19665/j.issn1001-2400.2022.03.024

西安电子科技大学学报 ›› 2022, Vol. 49 ›› Issue (3): 213-221.doi: 10.19665/j.issn1001-2400.2022.03.024

• 电子科学与技术&其他 • 上一篇下一篇

一种采用互连线电容耦合的线计算电路设计

李林¹(),张会红¹(),张跃军^1,²()

1.宁波大学信息科学与工程学院,浙江宁波 315211
2.复旦大学专用集成电路与系统国家重点实验室,上海 201210

收稿日期:2021-01-23 修回日期:2021-12-03 出版日期:2022-06-20 发布日期:2022-07-04
通讯作者: 张会红
作者简介:李林(1997—),男,宁波大学硕士研究生,E-mail: lilin20211@163.com|张跃军(1982—),男,副教授,博士,E-mail: zhangyuejun@nbu.edu.cn
基金资助:
国家自然基金(61871244);国家自然基金(61874078);专用集成电路与系统国家重点实验室开放研究课题基金(2019KF002);宁波市公益性计划项目(202002N3134);宁波市科技计划项目(202003N4107);宁波大学研究生SRIP项目(2020SRIP1320);宁波大学研究生科研创新基金(IF2021158)

Design of the line calculation circuit based on capacitive coupling of interconnection lines

LI Lin¹(),ZHANG Huihong¹(),ZHANG Yuejun^1,²()

1. Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China
2. State Key Laboratory of ASIC & System,Fudan University,Shanghai 201210,China

Received:2021-01-23 Revised:2021-12-03 Online:2022-06-20 Published:2022-07-04
Contact: Huihong ZHANG

摘要/Abstract

摘要：

随着集成电路工艺节点的不断推进,互连线间的寄生效应越来越明显。互连线已经成为制约提高芯片计算能力的关键因素之一,考虑将互连线作为逻辑计算的设计方法引起设计者的广泛关注。通过对互连线间电容耦合效应的研究,提出一种采用金属互连线间的确定性信号干扰来进行逻辑计算的电路设计方案。该方案首先分析金属互连线间电容耦合关系,构建电容耦合模型。然后利用纳米金属线构成耦合电容,调节干扰线与受扰线之间的耦合强度以及调整反相器阈值,设计与非、或非、异或、同或逻辑,在此基础上实现互连线电容耦合的3线-8线译码器。最后,采用台积电65 nm互补金属氧化物半导体工艺,Cadence Spectre环境下仿真验证,结果表明所设计的线计算电路功能正确。与台积电65 nm工艺库的标准单元相比,二输入线计算与非门使用的晶体管数量减少25%,二输入线计算同或门的功耗减少29.1%,四输入线计算与非门的面积和功耗延时积分别减少46.4%和55%。因此,线计算逻辑门具有低硬件开销特性,提供了密集实现数字集成电路的新途径,有利于芯片向小型化发展。

关键词: 电容耦合, 金属互连线, 线计算, 逻辑门, 译码器

Abstract:

With the continuous development of integrated circuit technology nodes,the influence of the parasitic effect between interconnects becomes more and more obvious.The interconnection line has become one of the key factors restricting the ability of chip computing,and the design method of using the interconnection line as logical calculation has aroused the designer's wide concern.Based on the study of the coupling effect of capacitance between metal interconnectors,a circuit scheme which uses the deterministic signal interference between metal interconnectors to carry out logic calculation is proposed.First,the capacitive coupling relationship between metal interconnections is analyzed to construct a capacitive coupling model.Then nano metal wires are used to form coupling capacitors,and further to design NAND,NOR,XOR and XNOR gates by adjusting the coupling strength between the interference line and the victim line and adjusting the inverter threshold.After that,a 3-wire-8-wire decoder based on capacitive coupling of interconnection lines is realized.Finally,by using TSMC 65 nm CMOS technology for simulation verification under Cadence Spectre environment,the results show that the designed line calculation circuit functions correctly.Compared with the standard unit of the TSMC 65 nm technology library,the number of transistors used in the two-input line calculation NAND is reduced by 25%,the power consumption of the two-input line calculation XNOR is reduced by 29.1%,and the area and power delay product of the four-input line calculation NAND are reduced by 46.4% and 55%,respectively.Therefore,the line calculation logic gate has the characteristics of a low hardware overhead,thus providing a new way to realize digital integrated circuits intensively,which is conducive to the miniaturization of chips.

Key words: capacitive coupling, metal interconnection line, line calculation, logic gate, decoder

中图分类号:

TN402

李林,张会红,张跃军. 一种采用互连线电容耦合的线计算电路设计[J]. 西安电子科技大学学报, 2022, 49(3): 213-221.

LI Lin,ZHANG Huihong,ZHANG Yuejun. Design of the line calculation circuit based on capacitive coupling of interconnection lines[J]. Journal of Xidian University, 2022, 49(3): 213-221.

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参考文献 19

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来源	电路	工艺 /nm	晶体管数量/个	面积 /μm²	供电电压 /V	平均功耗 /μW	传输延迟 /ps	功耗延时积 /aJ	线计算
文献[18]	NAND	90	9		0.3		180.0		否
文献[18]	NOR	90	9		0.3		187.5		否
文献[19]	NOR	90	20		0.3		50.0		否
	ND2D0	65	4	1.440	1.2	0.60	12.5	7.500	否
台积电65 nm	NR2D0	65	4	1.440	1.2	0.71	14.0	9.940	否
工艺库	XNR2D0	65	12	3.600	1.2	2.85	50.0	142.500	否
	ND4D0	65	8	2.520	1.2	1.30	28.5	37.050	否
	ND2D0	65	3	1.350	1.2	0.47	6.5	3.055	是
	NR2D0	65	3	1.350	1.2	0.91	29.5	26.845	是
笔者所提	XOR2D0	65	8	3.708	1.2	2.25	113.0	254.250	是
	XNR2D0	65	8	3.708	1.2	2.02	26.0	52.520	是
	ND4D0	65	3	1.350	1.2	1.19	14.0	16.660	是
	3线-8线译码器	65	47	22.104	1.2	17.06	87.0	1 484.220	是

一种采用互连线电容耦合的线计算电路设计

Design of the line calculation circuit based on capacitive coupling of interconnection lines

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