组相联可自适应扩展的缓存架构及其性能分析

doi:10.19665/j.issn1001-2400.20240101

摘要/Abstract

摘要：

在现代处理器体系架构中,缓存是解决存储墙瓶颈的重要手段,但是缓存访问需求是随程序甚至是程序片段的切换而变化的,这导致传统的固定参数配置的缓存架构难以在长时间或在程序间依然保持高效性能。文中提出一种缓存组相联度的自适应扩展方法,能根据程序运行时缓存组活跃状态,利用短时非活跃缓存组的存储空间,来扩展当前活跃缓存组的组相联数目,并可实时动态调整组与组之间的扩展互联关系,有效提升缓存空间的整体利用效率。文中在Gem5软件中对所提出的缓存组相联自适应扩展架构进行了仿真,并基于SPEC CPU 2017 基准测试集进行了性能测试,结果显示所提方法明显改善了缓存组访问的均匀性,对典型程序缓存组使用频次的均匀性最大提升23.14%左右,降低缓存访问缺失数最大可达54.2%。硬件实现和仿真结果显示,与HY-Way等低功耗可重构缓存架构相比,文中所述缓存架构资源消耗减少了7.66%以上,在嵌入式处理器设计中有较大的应用价值。

关键词: 组相联存储, 缓存架构, 组扩展, 组利用率, 性能仿真

Abstract:

In modern processor architectures,caching is an important method to solve the bottleneck of the memory wall.However,the requirement of cache access changes with the switching of the program or even a program fragment,which makes it difficult for traditional fixed-parameter configuration cache architectures to maintain a stable and efficient performance for a long time or between programs.This paper proposes an adaptively extended method for cache set associativity,which can use a short-term inactive cache set to expand the number of set associations of the current active cache set while the program is running,dynamically adjust the extended interconnection relationship between cache sets in real-time,and effectively improve the overall utilization efficiency of cache storage space.In this paper,the proposed cache architecture is simulated by Gem5 software,and the performance test is carried out based on the SPEC CPU 2017 benchmark.Simulation results show that the proposed method significantly improves the uniformity of cache set access with a maximum rate of about 23.14% for a typical program,and improves the reduction in missing ratio to a maximum of 54.2%.Hardware implementation and simulation results show that compared to low-power reconfigurable cache architectures such as HY-Way architecture,the proposed cache architecture reduces resource consumption by more than 7.66%,which has a significant application value in embedded processor designs.

Key words: associative storage, cache architecture, way extended, set utilization, performance simulation

中图分类号:

周昱, 于宗光, 高杨, 邵健, 罗庆. 组相联可自适应扩展的缓存架构及其性能分析[J]. 西安电子科技大学学报, 2024, 51(5): 71-81.

ZHOU Yu, YU Zongguang, GAO Yang, SHAO Jian, LUO Qing. Set associativity adaptively extended cache architecture and performance analysis[J]. Journal of Xidian University, 2024, 51(5): 71-81.

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配置	参数
处理器系统	指令集:RISC-V
	核数目:单核
	缓存级数:一级缓存
处理器核	指令发射:单指令发射
	执行模式:顺序执行
	分支预测:不使用
L1 D-Cache	缓存容量:32KB
	组相联度:4路
	缓存块大小:32B
	组替换策略:LRU
	缓存架构:传统缓存架构、HY-Way架构、E-Way缓存架构

序号	测试项	传统缓存架构缺失数	E-Way缓存架构缺失数	性能提升/%
1	500.perlbench	7 727	7697	0.39
2	502.gcc	84 044	82 577	1.75
3	503.bwaves	3 133 258	1 435 019	54.20
4	505.mcf	73 972	74 003	-0.04
5	508.namd	6 947	6 955	-0.12
6	519.lbm	1 246 995	1 246 995	0.00
7	521.wrf	816 117	783 797	3.96
8	527.cam4	169 791	169 921	-0.08
9	531.deepsjeng	1 224 844	1 224 844	0.00
10	541.leela	72 973	72 784	0.26
11	548.exchange2	2 544	2 542	0.08
12	549.fotonik3d	2 099	2 022	3.67

组相联度	测试项
	505.mcf		508.namd		527.cam4
	传统缓存架构	E-Way缓存架构	传统缓存架构	E-Way缓存架构	传统缓存架构	E-Way缓存架构
1(直接映射)	96 449	83 467	9 384	8 039	20 1901	192 967
2	75 172	74 737	7 426	7 402	17 5244	173 284
4	73 972	74 003	6 947	6 955	16 9791	169 921
8	73 939	74 065	6 751	6 814	16 9131	169 926
16	73 938	74 325	6 656	6 702	16 9146	169 862
1 024(全相联)		73 938	6 607		16 9138

资源类型	传统缓存架构	基于HY-Way架构^[7]	文中E-Way
LUT	1 057.0	1 489.0	1 320.0
FF	522.0	544.0	641.0
BRAM(36 Kb)	66.0	70.0	68.5
Fmax/MHz	111.7	100.5	110.8

	模块	传统缓存架构	HY-Way^[7]缓存架构			E-Way缓存架构
Tag组	状态标志位	4 b	4 b	4 b		5 b
	Tag位	TAG_LENGTH	TAG_LENGTH	TAG_LENGTH-1		TAG_LENGTH
	FPTR			INDEX_LEGTH-1
	Tag组数量	SET_NUM*ASSOC	SET_NUM*ASSOC/4	SET_NUMASSOC3/4		SET_NUM*ASSOC
Data组	状态标志位			3 b
	Data位	LINE_SIZE	LINE_SIZE	LINE_SIZE		LINE_SIZE
	RPTR			INDEX_LEGTH+1
	Reuse Count Table			2 b
	Data组数量	SET_NUM*ASSOC	SET_NUM*ASSOC/2	SET_NUM*ASSOC/2		SET_NUM*ASSOC
Ext组	Set LRU					1 b
	extState					2 b
	extIndex					INDEX_LEGTH
	Ext组数量					SET_NUM
合计b		293 888	320 256		297 728