90nm CMOS工艺下3×V<sub>DD</sub>容限静电检测电路

90nm CMOS工艺下3×V_DD容限静电检测电路

杨兆年;刘红侠;朱嘉

3×V_DD-tolerant ESD detection circuit in a 90nm CMOS process

YANG Zhaonian;LIU Hongxia;ZHU Jia

J4 . 2015, (1): 56 -61+206 . DOI: 10.3969/j.issn.1001-2400.2015.01.009