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A new motion estimation algorithm based on hardware implementation and its VLSI design

SONG Rui;ZHAO Bo;XIAO Song

  

  1. State Key Lab. of Integrated Service Networks, Xidian Univ., Xi’an 710071, China
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-04-20 Published:2006-04-20

Abstract: A new pyramid motion estimation algorithm and its VLSI architecture are proposed based on the demand for hardware implementation of a video encoder. The computational load is reduced by the method of a pyramidal sample in searching positions. Redundant computation of 8×8 or 4×4 blocks is removed after macro blocks for the Sum of Absolute Difference(SAD) of sub-block are calculated directly in the last layer of integral search. During hardware implementation processing, data stream access mode is revised, and parallel process efficiency is impoved as well. After positions sampling, each layer has a similar architecture, and hareware resource is saved significantly by use of the common module. Simulation results on MPEG-4 SP show that although the new pyramid algorithm is 0.02dB lower than full search in PSNR, the process load and hardware resource occupancy are 7% and 25%, respectively, that of full search, which will meet the requirements for real time applications.

Key words: motion estimation, new pyramid algorithm, hardware reuse, real time process

CLC Number: 

  • TN919.18