面向测试的SOC核间互连网络约简算法

J4 ›› 2009, Vol. 36 ›› Issue (5): 871-876+956.

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Study of the reduction algorithm of SOC inter-core interconnects for testing

SHANG Yu-ling^1,2;LI Yu-shan¹

(1. Research Inst. of Electronic CAD, Xidian Univ., Xi'an 710071， China;
2. School of Electronic Eng., Guilin Univ. of Electronic Tech., Guilin 541004， China)

Received:2009-03-18 Online:2009-10-20 Published:2009-11-30
Contact: SHANG Yu-ling E-mail:syl@guet.edu.cn

Abstract

Abstract:

With the manufacturing technology and operation frequency of VLSI entering the era of DSM and GHz, the crosstalk of SOC inter-core interconnects can not be ignored anymore. A reduction algorithm for core-external interconnect is presented based on characteristics of the interconnect bus of SOC. Any topology of inter-core interconnects is described first and an interconnect relationship tree is built. Unwanted aggressive interconnects could be cut off according to the accuracy of test. Interconnects with the tri-state and bi-direction driving source are sifted according to the mutex algorithm. Test patterns are generated for these interconnects after sifting according to the TPG algorithm. The test set is decreased and test efficiency is improved.

Key words: system on chip, inter-core interconnects, tri-state bi-directed nets

CLC Number:

TN407

SHANG Yu-ling;LI Yu-shan. Study of the reduction algorithm of SOC inter-core interconnects for testing[J].J4, 2009, 36(5): 871-876+956.

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Study of the reduction algorithm of SOC inter-core interconnects for testing

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