多端口存储器控制器IP核的研究

doi:10.3969/j.issn.1001-2400.2010.01.025

J4 ›› 2010, Vol. 37 ›› Issue (1): 142-147.doi: 10.3969/j.issn.1001-2400.2010.01.025

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Research on the multiport memory controller IP core

MA Qin-sheng¹;CAO Yang^1,2;YANG Jun¹;ZHANG Ning¹

(1. School of Electronic Information, Wuhan Univ., Wuhan 430079， China;
2. State Key Lab. of Software Eng., Wuhan Univ., Wuhan 430072， China)

Received:2008-08-27 Online:2010-02-20 Published:2010-03-29
Contact: MA Qin-sheng E-mail:maqinsheng@hotmail.com

Abstract

Abstract:

In order to improve the memory bandwidth for masters accessing external memory in the SoC system, a multi-port memory controller IP core based on the AHB bus is developed. Also, an arbitration strategy for the early arbitration and request waiting priority is proposed. A number of masters in this IP core are requested to access the external memory through a number of ports. The arbitration selects the highest-priority port in the early arbitration moment and sets the request waiting time for the other ports that are not allowed the access request . The early arbitration moment occurs before the completion for the current read/write operations. When the next early arbitration moment happens, the arbitration arbitrates these timeout ports in preference. The results of simulation and hardware verification indicate that the maximum memory bandwidth is about 532MB/s and that the maximum bus utilization rate is about 90％.

Key words: application specific integrated circuits, intellectual property, logic design, control equipment, data storage equipment, reusability, multiport;arbiter

MA Qin-sheng;CAO Yang;YANG Jun;ZHANG Ning. Research on the multiport memory controller IP core[J].J4, 2010, 37(1): 142-147.

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Research on the multiport memory controller IP core

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