采用EMS算法的多元LDPC译码器的FPGA实现

doi:10.3969/j.issn.1001-2400.2011.05.005

Abstract

Abstract:

Due to the high resources demand during the decoding process of non-binary LDPC codes, a non-binary LDPC decoder based on the EMS (Extended Min-Sum) algorithm is proposed. The messages are updated iteratively in the block unit, and the flooding schedule is utilized in this proposed decoder. To reduce the storage resources and logical resources, the messages are first contracted in length. Then, the resources are multiplexed between the process of check nodes updating and that of variable nodes updating by the time difference. An FPGA chip for decoding an irregular non-binary LDPC over GF(64) of length 1044bit has been developed based on the Xilinx XC4VLX60 FPGA device. Compared to the existing solutions, about 54% storage resources and logical resources can be saved. Meanwhile, the decoding speed and throughput can be greatly improved.

Key words: non-binary LDPC codes, Galois fields, FPGA, decoder

CLC Number:

TN911.21

HE Guanghua;BAI Baoming;LI Bo;LIN Wei. FPGA implementation of a non-binary LDPC decoder using the EMS algorithm[J].J4, 2011, 38(5): 27-33.

References

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FPGA implementation of a non-binary LDPC decoder using the EMS algorithm

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