[1] Li Erping, Wei Xingchang, Cangellaris A C, et al. Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects[J]. IEEE Trans on Electromagnetic Compatibility, 2010, 52(2): 248-265.
[2] 丁同浩, 李玉山, 张伟, 等. 非理想互连的传输线模型及串扰分析[J]. 西安电子科技大学学报, 2010, 37(4): 694-699.
Ding Tonghao, Li Yushan, Zhang Wei, et al. Transmission Line Model and Crosstalk Analysis of Non-ideal Interconnect[J]. Journal of Xidian University, 2010, 37(4): 694-699.
[3] 董刚, 杨杨, 柴常春, 等. 考虑工艺波动的两相邻耦合RC互连串扰噪声估计[J]. 西安电子科技大学学报, 2010, 37(6): 1082-1087.
Dong Gang, Yang Yang, Chai Changchun, et al. Crosstalk Noise Estimation of Two Adjacent RC Interconnects with Process Variations[J]. Journal of Xidian University, 2010, 37(6): 1082-1087.
[4] 李丽平, 李玉山, 王崇剑. 防护线减小微带线间串扰的FDTD分析[J]. 电子与信息学报, 2006, 28(3): 574-576.
Li Liping, Li Yushan, Wang Chongjian. FDTD Analysis of the Crosstalk Reduction with Guard Trace between Microstrips[J]. Journal of Electronics & Information Technology, 2006, 28(3): 574-576.
[5] Mbairi F D, Siebert W P, Hesselbom H. High-frequency Transmission Lines Crosstalk Reduction Using Spacing Rules[J]. IEEE Trans on Components and Packaging Technologies, 2008, 31(3): 601-610.
[6] Lee K, Jung H K, Chi H J, et al. Serpentine Microstrip Lines with Zero Far-end Crosstalk for Parallel High-speed DRAM Interfaces[J]. IEEE Trans on Advanced Packaging, 2010, 33(2): 552-558.
[7] Swaminathan M, Kim J, Novak I, et al. Power Distribution Networks for System-on-package: Status and Challenges[J]. IEEE Trans on Advanced Packaging, 2004, 27(2): 286-300.
[8] Gu Q, Tassoudji A, Poh S Y, et al. Coupled Noise Analysis for Adjacent Vias in Multilayered Digital Circuits[J]. IEEE Trans on Circuits Systems Part I: Regular Papers, 1994, 41(12): 796-804.
[9] Lee S H, Jin Jianming. Efficient Full-wave Analysis of Multilayer Interconnection Structures Using a Novel Domain Decomposition-model-order Reduction Method[J]. IEEE Trans on MTT, 2008, 56(1): 121-130.
[10] Swaminathan M, Chung D, Grivet-Talocia S, et al. Designing and Modeling for Power Integrity[J]. IEEE Trans on EMC, 2010, 52(2): 288-310.
[11] Heinrich G, Dickmann S. On the Coupling between the Signal Layers and the Power-bus on Multilayered PCBs[C]//EMC 2009 IEEE International Symposium on. New York: IEEE Service Center, 2009: 39-44.
[12] Okoshi T. Planar Circuits for Microwaves and Light Waves[M]. Minich: Springer, 1985.
[13] Zhang Y, Fan J, Selli G, et al. Analytical Evaluation of Via-plate Capacitance for Multilayer Printed Circuit Boards and Packages[J]. IEEE Trans on MTT, 2008, 56(9): 2118-2128.
[14] Ndip I, Ohnimus F, Lobbicke K, et al. Modeling, Quantification, and Reduction of the Impact of Uncontrolled Return Currents of Vias Transiting Multilayered Packages and Boards[J]. IEEE Trans on EMC, 2010, 52(2): 421-435.
[15] Lei G T, Techentin R W, Gilbert B K. High-frequency Characterization of Power/ground Plane Structures[J]. IEEE Trans on MTT, 1999, 47(5): 562-569.
[16] 周子琛, 潘峰, 申振宁. 高速嵌入式系统中电源噪声抑制方法[J]. 电讯技术, 2010, 50(10): 103-107.
Zhou Zichen, Pan Feng, Shen Zhenning. Power Bus Noise Suppression in High Speed Embedded Systems[J]. Telecommunication Engineering, 2010, 50(10): 103-107.
[17] Wu T L, Chuang H H, Wang T K. Overview of Power Integrity Solution on Package and PCB: Decouping and EBG Isolation[J]. IEEE Trans on EMC, 2010, 52(2): 346-356. |