[1] KOCHER P C. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems[C]//Lecture Notes in Computer Science: 1109. Berlin: Springer Verlag, 1996: 104-113.
[2] SCHINDLER W. Exclusive Exponent Blinding Is Not Enough to Prevent Any Timing Attack on RSA[J]. Journal of Cryptographic Engineering, 2016, 6(2): 101-119.
[3] BRUMLEY D, BONEH D. Remote Timing Attacks Are Practical[J]. Computer Networks, 2005, 48(5): 701-716.
[4] 崔西宁, 杨经纬, 叶宏, 等. 椭圆曲线密码的优化设计方法[J]. 西安电子科技大学学报, 2015, 42(1):69-74.
CUI Xining, YANG Jingwei, YE Hong, et al. Optimized Design Method on Elliptic Curve Cryptography[J]. Journal of Xidian University, 2015, 42(1): 69-74.
[5] WAUGH R. Could a Vulnerable Computer Chip Allow Hackers to Down a Boeing 787? ‘Back Door’ Could Allow Cyber-criminals a Way in[EB/OL]. [2016-12-04]. http: //www. dailymail. co. uk/sciencetech/article-2152284/.
[6] ADEE S. The Hunt for the Kill Switch[J]. IEEE Spectrum, 2008, 45(5): 34-39.
[7] HU W, MAO B, OBERG J, et al. Detecting Hardware Trojans with Gate-level Information-flow Tracking[J]. Computer, 2016, 49(8): 44-52.
[8] 张国栋, 刘强, 张齐军. 用于FPGA IP保护的低成本高性能PUF设计[J]. 西安电子科技大学学报, 2016, 43(6): 97-102.
ZHANG Guodong, LIU Qiang, ZHANG Qijun. Low Cost and High Performance RO-PUF Design for IP Protection of FPGA Implementations[J]. Journal of Xidian University, 2016, 43(6): 97-102.
[9] OBERG J, MEIKLEJOHN S, SHERWOOD T, et al. Leveraging Gate-level Properties to Identify Hardware Timing Channels[J]. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2014, 33(9): 1288-1301.
[10] MU D J, HU W, MAO B L, et al. A Bottom-up Approach to Verifiable Embedded System Information Flow Security[J]. IET Information Security, 2014, 8(1): 12-17.
[11] PETER S, GIVARGIS T. Towards a Timing Attack Aware High-level Synthesis of Integrated Circuits[C]//Proceedings of the 34th IEEE International Conference on Computer Design. Piscataway: IEEE, 2016: 452-455.
[12] ZHANG D, WANG Y, SUH G E, et al. A Hardware Design Language for Timing-sensitive Information-flow Security[J]. ACM SIGPLAN Notices, 2015, 50(4): 503-516.
[13] KOPF B, DURMUTH M. A Provably Secure and Efficient Countermeasure against Timing Attacks[C]//Proceedings of the IEEE Computer Security Foundations Symposium. Piscataway: IEEE, 2009: 324-335.
[14] KASTNER R, HU W, ALTHOFF A. Quantifying Hardware Security Using Joint Information Flow Analysis[C]//Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition. Piscataway: IEEE, 2016: 1523-1528.
[15] OBERG J, HU W, IRTURK A, et al. Information Flow Isolation in I2C and USB[C]//Proceedings of the Design Automation Conference. Piscataway: IEEE, 2011: 254-259.
[16] COVER T M, THOMAS J A. Elements of Information Theory[M]. Second Edition. Hoboken: Wiley-Blackwell, 2006: 13-54. |