Abstract: A model of drain current degradation of DSM NMOSFET devices induced by HCI and implementation in circuit reliability simulation is proposed. The model unifies the subthreshold, linear and saturation regions into a continuous equation, which a voids the simulation convergence problem due to the discontinuous model. And the gate bias dependency in the subthreshold region is also modeled for improved accuracy. The model has a high accuracy for SMIC on their 0.25μm technologies. The simulation method in this paper has been applied to the XDRT circuit reliability simulator.

Key words: deep submicron NMOSFET, HCI degradation, ΔI_d model, HCI circuit reliability simulation