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A novel BIST technique for multipliers cores

LEI Shao-chong;SHAO Zhi-biao;LIANG Feng   

  1. School of Electronics and Information Engineering, Xi′an Jiaotong Univ., Xi′an 710049, China
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-10-20 Published:2006-10-30

Abstract: A novel built-in self-test (BIST) scheme for multiplier cores is proposed. The scheme combines the advantages of C-testable and pseudorandom testing, and the designed test circuit imposes small extra hardware, which is less than that of the pseudorandom testing circuit by 56%. In test generation, the proposed method uses the unique assigning technique to achieve a very small test set with fault coverage higher than 99%. The generated test set is reordered and compressed by our developed program, and its switching activities and width are drastically reduced. Based on the above results, a low cost circuit can be easily implemented. Experimental results show that the designed BIST circuits are superior to other BIST circuits in hardware, power consumption and test time.

Key words: low cost, multiplier, C-testable, built-in self-test

CLC Number: 

  • TN47