基于3DES的跳频序列族构造方法的VLSI实现

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基于3DES的跳频序列族构造方法的VLSI实现

LI Zan1;CAI Jue-ping2;JIN Li-jun1;CHANG Yi-lin1

(1. State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an 710071, China;
2. Dept. of Electronic Engineering, Shanghai Jiaotong Univ., Shanghai 200030, China)

Received:1900-01-01 Revised:1900-01-01 Online:2004-08-20 Published:2004-08-20

Abstract

Abstract: This paper deals with the VLSI realization of the frequency hopping sequences generator based on the encrypted mechanism of 3DES block ciphers. The VLSI architecture design of the algorithm is efficiently implemented using the VHDL language adopting the method of the Finite State Machine. Characterized by stability, fast operation and flexible data input, the realized generator can satisfy the requirement of 2000hops/s with the system clock ranging within 1.5MHz~24MHz, which has been used in fast FH radios.

Key words: block cipher, FH sequences, VHDL, VLSI

CLC Number:

TN914.41

LI Zan1;CAI Jue-ping2;JIN Li-jun1;CHANG Yi-lin1.

基于3DES的跳频序列族构造方法的VLSI实现

[J].J4, 2004, 31(4): 501-504.

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基于3DES的跳频序列族构造方法的VLSI实现

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