Abstract: With the segmentation structure and low-swing circuit of the integrated circuit interconnect, an optimal design method is developed for efficiently solving the challenge of the FPGA energy delay product. OPtimizing the segmentation number of the FPGA interconnect with transmission line effects, the driving unit and receiving unit of the low-swing circuit are respectively connected to the input and output of the interconnect, and optimal size repeaters are inserted in the segmented interconnect. Both theoretical and experimental results show that the improvement of the FPGA energy delay product with this new technique is about an order of magnitude when compared to existing commerical architectures while keeping the good area performance of FPGA.

Key words: FPGA interconnect, RLC model, segmentation structure, low-swing circuit, energy delay product