一种基于SOC应用的Rail-to-Rail运算放大器IP核

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A rail-to-rail operational amplifier IP core for SOC application

ZHAI Yan;YANG Yin-tang;ZHU Zhang-ming;WANG Fan

Ministry of Edu. Key Lab. of Wide Band-Gap Semiconductor Materials and Devices,Xidian Univ., Xi′an710071， China

Received:1900-01-01 Revised:1900-01-01 Online:2005-02-20 Published:2005-02-20

Abstract

Abstract: Based on SOC application, a Rail-to-Rail operational amplifier IP core with a low-power and a high gain is
presented. The operational amplifier will be realized in the CSMC 0.6μm DPDM CMOS process. The whole circuit is simulated with the BSIM3V3 Spice model in Hspice. With a single power supply of 5V in simulation, it is shown that the Rail-to-Rail operational amplifier has an open loop gan of 107. 8dB, a phase margin of 62. 4 degrees and a unit gain bandwidth of 4.3MHz, with the static power dissipation being only 0.34mW.

Key words: Rail-to-Rail, CMOS, operational amplifier, IP core, SOC

CLC Number:

TN402

ZHAI Yan;YANG Yin-tang;ZHU Zhang-ming;WANG Fan.

A rail-to-rail operational amplifier IP core for SOC application

[J].J4, 2005, 32(1): 112-115.

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A rail-to-rail operational amplifier IP core for SOC application

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