As FPGAs have been adopted in many electronic system designs, intellectual property (IP) protection of FPGA implementations has become one of the major concerns in industry. The ring oscillator-based physical unclonable function (RO-PUF) has been investigated for IP authentication of FPGA implementations. However, integrating RO-PUF into FPGA implementations for practical applications still faces challenges: (1) it always introduces considerable hardware overheads; and (2) the limited set of challenge-response pairs (CRPs) due to limited circuit resources may not authenticate a large population of FPGA implementations with a small error. To address these issues, this paper first proposes an effective technique, logic fusion. It combines the RO logic of the PUF with the normal circuit logic, without increasing logic resource usage in FPGAs. Second, a post-processing procedure is exploited to expand the set of CRPs from the designed RO-PUF. Experimental results show that the reliability, randomness and uniqueness metrics of the designed RO-PUF are 99.97％, 50.37％ and 49.83％, respectively. Compared with the existing RO-PUF design techniques, the area overhead can be reduced by 45％ with the same performance.
