RM逻辑伪装门的硬件混淆设计

doi:10.19665/j.issn1001-2400.2020.02.018

Abstract

Abstract:

To improve the ability of the integrated circuit to resist reverse engineering, we study the logic obfuscation technology and propose a logic obfuscation scheme based on the Reed-Muller camouflage gate. First, different virtual hole configurations are adopted to realize XOR/AND logical functions on the same layout, and feature information of the logical obfuscating circuit is extracted to make the standard cell physical library. Then, the obfuscation physical library is applied in the circuit netlist by the random insertion algorithm. Finally, the ISCAS benchmark is used to verify the effectiveness of the proposed scheme. Simulation results reveal that the similarity of the Reed-Muller logic camouflage layout is improved by 14.36%, and that the power consumption overhead is about 2.36% under the larger scale benchmark. Experiment indicates that the designed obfuscation gate can effectively resist reverse engineering and improve the hardware security of the circuit.

Key words: hardware security, Reed-Muller logic, logical obfuscation, reverse engineering

CLC Number:

TN402

WU Qiufeng,ZHANG Yuejun,WANG Pengjun,ZHANG Huihong. Hardware obfuscation design of the RM logical camouflage gate[J].Journal of Xidian University, 2020, 47(2): 135-141.

Figures/Tables 9

References 19

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功能	通孔
功能	真实	虚拟
异或门	1 2 4 5 6 7 8 11	3 9 10 12
与门	1 3 6 8 9 10 11 12	2 4 5 7

文献	混淆方法	工艺/nm	面积开销/%	功耗开销/%	延时开销/%	功耗延时积/%
[10]	电路伪装		66.02	66.89	36.23	24.23
[18]	布尔逻辑锁	台积电65	8.03	28.76	26.56	7.64
[19]	混淆状态机	台积电65	23.00	11.00	19.00	2.09
笔者提出	RM逻辑锁	台积电65	10.73	5.11	47.23	2.41

Hardware obfuscation design of the RM logical camouflage gate

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