SM4算法的FPGA优化实现方法

doi:10.19665/j.issn1001-2400.2021.03.020

Abstract

Abstract:

Data encryption is one of the important means to ensure information security.In data encryption,the SM4 algorithm is widely used by considering its advantages of strong security,high efficiency,and easy hardware implementation.Current researchesfocus on hardware-feature based implementation to improve the cost and performanceof the SM4 algorithm.Four sets of hardware architecture are proposed for the SM4 algorithm and implemented on XILINX KINTEX-7 FPGA.The circular architecture is optimized for resource saving,which consumes 193 SLICE,and has a throughput of 1.27 Gb/s;the pipeline architecture is based on the LUT,BRAM,BRAM+REGISTER method implementation.According to different application scenarios,three solutions can be optimized in terms of resource consumption such as lookup tables,registers,and block memory,with the throughput reaching 42.10 Gb/s.

Key words: SM4, field programmable gate array, architecture optimization, hardware implementation

CLC Number:

TP309.7

HE Shiyang,LI Hui,LI Fenghua. Optimization and implementation of the SM4 on FPGA[J].Journal of Xidian University, 2021, 48(3): 155-162.

Figures/Tables 11

符号	说明
$Z 2 e$	表示比特e的向量集,Z $232$ 中的元素称为字,Z $28$ 中的元素称为字节
Sbox(·)	表示8输入8输出的S盒,用于非线性置换
⊕	表示32 bit的异或运算
<<<i	表示32 bit的循环左移计算
M_K	表示加密密钥,长度为128 bit
$r k i$ (i=0,…,31)	表示轮密钥,长度为32 bit
$c k i$ (i=0,…,31)	表示系统参数,长度为32 bit

References 10

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硬件架构	查找表个数	融发器个数	逻辑单元个数	存储器个数	运行频率/MHz	吞吐量/(Gb·s^-1)
循环型	697	268	193	0	333	1.27
LUT流水线型	7 466	5 158	2 296	0	250	30.52
BRAM流水线型	2 261	4 945	1 353	33	227	27.74
BRAM+REGISTER流水线型	3 213	7 736	1 580	33	333	42.10

方案	资源消耗	运行频率/MHz	吞吐量/(Gb·s^-1)	硬件设备
文献[6]	1 552 ALM	139	0.54	StraitxII
文献[7]	380 SLICE	185	0.74	Virtex-4
文献[9]	687 LUT 448 FF	210	0.82	StraitxIV
文中方案	697 LUT 268 FF	333	1.27	Kintex-7

方案	资源消耗	运行频率/MHz	吞吐量/(Gb·s^-1)	硬件设备
文献[6]	8 373 ALM	162	20.74	StraitxII
文献[7]	9 500 SLICE	190	24.32	Virtex-4
文献[9]	7 667 LUT 5 438 FF	212	27.15	StraitxIV
LUT流水线型	7 466 LUT 5 158 FF	250	30.52	Kintex-7
BRAM流水线型	2 261 LUT 4 945 FF 33 BRAM	227	27.74	Kintex-7
BRAM+REGISTER流水线型	3 213 LUT 7736 FF,33 BRAM	344	42.10	Kintex-7

Optimization and implementation of the SM4 on FPGA

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