J4 ›› 2011, Vol. 38 ›› Issue (6): 140-145.doi: 10.3969/j.issn.1001-2400.2011.06.023

• Original Articles • Previous Articles     Next Articles

Research on the test and verification system of the ARINC 659 fault-tolerant backplane data bus

ZHANG Ximin1,2;WEI Ting1
  

  1. (1. Aeronautics Computing Technique Research Institute, Xi'an  710068, China;
    2. Research Inst. of Multimedia Technology, Xidian Univ., Xi'an  710071, China)
  • Received:2010-08-22 Online:2011-12-20 Published:2011-11-29
  • Contact: ZHANG Ximin E-mail:zczya@sohu.com

Abstract:

The ARINC 659 data bus is a high reliability and high-integrity avionic standard backplane bus designed to provide fault tolerance and robustness partition in time and memory space. It is a key component of the integrated modular avionics system. The ARINC 659 data bus is the property key technique of the Honeywell Company, and it places a stick embargo on the correlative productions for other companies especially for our country. In this paper, the independent innovative ARINC 659 data bus interface ASIC, which has a special microprocessor, and its Frame Description Language compiler are developed. The design and realization of the communication test platform are presented, which consists of the three complements: the ARINC 659 data bus interface card, the communication node controller and the communication test-bed of the data bus. The debug and test configurations of the hardware and software are explored. The methods are given to test and verify the function under the test environment according to the ARINC 659 Specification, and the result shows the correctness and integrity of the design. The research has been applied in the avionic safe critical systems, and the systems benefit from it with higher reliability and lower LLC.

Key words: ARINC 659, fault-tolerance, backplane data bus, interface chip design, test environment, function verification