10bit 100MS/s混合型模数转换器

doi:10.3969/j.issn.1001-2400.2018.03.015

Abstract

Abstract:

In order to improve the performance of the Analog-to-Digital Converter (ADC), a hybrid ADC has been designed which combines the Flash ADC and the Successive Approximation Register (SAR) ADC And a novel algorithm named Higher Capacitor Skipped or Reused (HCSR) is proposed to further improve the energy efficiency of the hybrid ADC. Theoretical analysis shows that the proposed switching scheme reduces the capacitor requirement by almost twofold and improves the average switching energy efficiency by 81.22％ compared with the Merged capacitor switching (MCS) algorithm. It is designed and simulated by SMIC 0.18μm technology The hybrid ADC achieves 75.879dB SFDR, 9.902bit ENOB, consumes 2.41mW and offers a good energy efficiency of 25.19fJ／conversion-step with the Nyquist input frequency at the sampling rate of 100MS／s. Simulation shows that the hybrid ADC which utilizes the proposed switching scheme achieves a perfect trade-off among speed, power, and area.

Key words: flash analog-to-digital converter, successive approximation register analog-to-digital converter, switching algorithm, higher capacitor skipped or reused

ZHANG Zhang;YU Wencheng;XIE Guangjun. 10bit 100MS/s Hybrid ADC[J].Journal of Xidian University, 2018, 45(3): 80-85+116.

References

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10bit 100MS/s Hybrid ADC

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