Abstract: Interconnect delay evaluation is always a crucial concern in the VLSI design. An interconnect line in a VLSI circuit is in general a tree pattern rather than a single line. An approach to analyzing RLC Interconnect tree delay based on "effective capacitance" is presented in this paper. This new method is compared with the equivalent Elmore delay, which shows that the relative error by the new method is less than that by the equivalent Elmore delay.

Key words: RLC interconnect tree delay, effective capacitance, RLC interconnect Π model, equivalent Elmore delay