Abstract: Based on the modified Euclid’s algorithm, a VLSI architecture is proposed, which only uses two folding calculating cells and three-stage pipeline processing architectures to improve its throughput. Also, a way is introduced to reduce the complexity and critical path delay of general finite multipliers by the transferring of field from the time domain to the composite domain. Based on the TSMC 0.18 standard cell library, the proposed RS decoder consists of about 20 614 gates for widely used RS(255,239) code, which reduces complexity by about 60％ compared with an existing architecture with systolic arrays when having the same error correction ability.

Key words: Reed-Solomon codes, pipeline architecture, Euclid algorithm, verilog HDL, VLSI