Abstract: A new optimized-approximate integer-to-integer wavelet transform of the JEPG2000 scheme is proposed. And from the hardware perspective, the corresponding line-based VLSI based on the lifting scheme is put forward. Considering that the dynamic range of the wavelet coefficients is limited, this scheme ensures higher precision of the wavelet transform and accordingly improves the quality of image compression by preserving efficiently fractions of wavelet coefficients in lifting steps. Thanks to the line-based architecture in hardware implementation, the horizontal transform and vertical transform can be executed in a parallel way. Experiments show that on a Xilinx FPGA marked XC2V3000, the architecture requires only 27％ resources and achieves a higher clock frequency up to 66MHz. Compared with other existing wavelet transform architectures, the proposed architecture not only advances performance of the integer-to-integer wavelet transform, with advantages of high parallelism and reduction in storage, but also guarantees total levels of the wavelet transform during the time T that an image is scanned line by line.

Key words: wavelet transforms, lifting scheme, optimized-approximate, VLSI circuits