Abstract: According to the problem of the significant increasing testing cost of VLSI caused by the significant increase in testing time, this paper proposes a novel approach to test compaction for scan circuits that use limited scan operations instead of full scan operations between test pairs. This leads to very aggressive compaction on the test application time cost under the same fault coverage. The experimental result of benchmark circuits shows that the test application time cost of the proposed method is about 50％ that of the conventional methods.

Key words: test application time, limited scan operation, static test compaction, heuristic methods