图像混合插值缩放IP核的VLSI设计

doi:10.3969/j.issn.1001-2400.2010.01.028

Abstract

Abstract:

In order to solve the problem of various input video sources displaying in flat panel display devices which have the fixed resolution without any distortion, an algorithm for image scaling based on mixed interpolation by bilinear and bicubic is proposed, and its corresponding hardware implementation is also presented. The image scaling IP core is designed by VLSI based on the mixed interpolation. The input video sources with various formats are supported by it, and the high-precision scaling function without external storage is implemented. As an embedded IP core, the image scaling core is verified to be correct in function in the digital video processing chip DTV100B. The mixed interpolation method is superior in image detail and definition preserving to bilinear interpolation, and its expense of internal memory resources is less than half that of bicubic interpolation.

Key words: image scaling, bilinear, bicubic, IP core, VLSI

GE Chen-yang;ZHENG Nan-ning;REN Peng-ju. VLSI design of the image scaling IP core with the mixed interpolation algorithm[J].J4, 2010, 37(1): 158-162.

References

［1］Lee Honam, Lee Bonggeun, Lee Youngho, et al. Optimized VLSI Design for Enhanced Image Downscaler ［C］//IEEE AP-ASIC. Cheju: IEEE, 2000: 139-142.
［2］葛晨阳, 徐维朴, 孙飞. IP复用技术的研究［J］. 微电子学, 2002, 32(4): 257-260.
Ge Chenyang, Xu Weipu, Sun Fei. A Study on IP Reuse Technology ［J］. Microelectronics, 2002, 32(4): 257-260.
［3］陈泽志, 吴成柯, 刘勇. 双三次B-样条平滑滤波算子的研究［J］. 西安电子科技大学学报, 2002, 29(2): 200-204.
Chen Zezhi, Wu Chengke, Liu Yong. Research on the Bicubic B-spline Smoothing Filter Operator ［J］. Journal of Xi Dian University, 2002, 29(2): 200-204.
［4］尹擎. 数字视频图像缩放IP核的设计与验证［D］. 西安: 西安交通大学, 2006.
Yin Qin. Design and Verification of Digital Video Scaling IP Core ［D］. Xi'an: Xi'an Jiaotong University, 2006.
［5］Genesis Microchip Corporation. Gm5010/5010-H Data Sheet ［CP/DK］. California: Genesis Microchip Corporation, 2002.
［6］Trumpion Microelectronics Corporation. ZUR AC2＆e Zoom Engine for TFT-LCD Monitor Data Sheet ［CP/DK］. Taibei: Trumpion Mmicroelectronics Corporation, 2002.
［7］Mstar Semiconductor Corporation. MST6M69L All-in-one LCD TV Controller Preliminary Data Sheet Version 0.1 ［CP/DK］. Taibei: Mstar Semiconductor Corporation, 2008.
［8］郑南宁, 尹擎, 李永, 等. 一种基于双三次插值的数字视频图像缩放的方法及其电路［P］. 中国: 200510096292.4, 2008-10-12.
Zheng Nanning, Yin Qin, Li Yong, et al. The Method and Circuit for Digital Video Scaling Based on Bicubic Interpolation［P］. China: 200510096292.4, 2008-10-12.
［9］西安交通大学SoC设计中心. 数字视频后处理芯片DTV100B数据手册［R］. 西安: 西安交通大学SoC设计中心, 2007.
SOC Design Center of Xi'an Jiaotong University. Digital Video Post-process Chip DTV100B Data Sheet ［R］. Xi'an.SOC Design Center of Xi'an Jiaotong University, 2007.
(2010, Vol.37, No.1, 158-162)

[1]	DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong. Highly efficient VLSI architecture for DWT with low-storage implementation [J]. Journal of Xidian University, 2016, 43(2): 35-40.
[2]	LI Xiaofeng;FENG Dazheng;HU Shukai. Low power Turbo decoder based on the state metric decimation and interpolation strategy [J]. J4, 2012, 39(3): 58-62+71.
[3]	XIE Yuanbin;SHI Jiangyi;HAO Yue. Improved modular exponentiation and VLSI implementation for RSA cryptosystem [J]. J4, 2011, 38(2): 129-134+179.
[4]	DENG Jun. Structure of the low-power interpolation filter and its VLSI implementation for all-digital receiver [J]. J4, 2010, 37(2): 320-325.
[5]	MING Yang1;ZHAN Yang2;WANG Yu-min2;PANG Liao-jun2. Improved certificateless signature scheme [J]. J4, 2008, 35(6): 1094-1099.
[6]	LEI Jie;KONG Fan-qiang;WU Cheng-ke;LI Yun-song. Hardware-oriented rate control algorithm for JPEG2000 and its VLSI architecture design [J]. J4, 2008, 35(4): 645-649.
[7]	GUO Jie;WU Cheng-ke;WANG Ke-yan;MA Jing;ZHANG Lei. Optimized-approximate integer-to-integer wavelet transform and its VLSI architecture of JPEG2000 codec [J]. J4, 2008, 35(2): 210-215.
[8]	ZHANG Jing-bo1;DAI Xian-ying2;ZHANG He-ming2;HU Hui-yong1;JIA Da-zhong1. Area-efficient high-speed VLSI design of the RS(255,239) decoder [J]. J4, 2008, 35(1): 116-120.
[9]	YANG Chen;MA Wen-ping;WANG Xin-mei. ID-based Group Key Distribution Scheme with Dynamic Joining [J]. J4, 2007, 34(7): 14-17.
[10]	CAO Xue-fei;ZENG Xing-wen;KOU Wei-dong;YU Yong. A novel anonymous authentication scheme over the insecure channel [J]. J4, 2007, 34(6): 877-880.
[11]	ZHANG Chuan-rong1;2;XIAO Guo-zhen1. Multi-signcryption scheme using identity and bilinear pairing [J]. J4, 2007, 34(2): 270-273.
[12]	SHI Ying-bo;LI Yun-song;ZHANG Jian-long. An efficient VLSI architecture of the CABAC decoder in H.264 [J]. J4, 2006, 33(6): 844-848.
[13]	ZHAO Chun-ming;GE Jian-hua;LI Xin-guo. Hidden authentication conditional oblivious transfer [J]. J4, 2006, 33(6): 849-852.
[14]	LIU Ying;HU Yu-pu;WANG Fei;LU Xiao-jun. An efficient ID-based threshold signature [J]. J4, 2006, 33(2): 311-315.
[15]	WEI Ling-bo;YANG Bo. An efficient anonymous fingerprinting scheme based on the bilinear Diffie-Hellman intractability assumption [J]. J4, 2005, 32(5): 794-797.

VLSI design of the image scaling IP core with the mixed interpolation algorithm

PDF (PC)

Like

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 15

Metrics

Comments

Recommended 0