J4 ›› 2011, Vol. 38 ›› Issue (2): 129-134+179.doi: 10.3969/j.issn.1001-2400.2011.02.023

• Original Articles • Previous Articles     Next Articles

Improved modular exponentiation and VLSI implementation for RSA cryptosystem

XIE Yuanbin;SHI Jiangyi;HAO Yue   

  1. (Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an  710071, China)
  • Received:2010-10-06 Online:2011-04-20 Published:2011-05-26
  • Contact: XIE Yuanbin E-mail:ybxie@mail.xidian.edu.cn

Abstract:

Modular multiplication and exponentiation severely restrict the RSA performance. The paper displays a modified Montgomery modular multiplication algorithm based on the two-level carry-save addition (CSA) tree. By inserted registers, the algorithm shortens the critical path and guarantees operands arriving at the CSA input ports simultaneously, which significantly improves the speed of modular multiplication. The modular-multiplication sequence is adjusted in modular exponentiation, which avoids most format conversion and reduces the conversion time. The proposed modular exponentiation circuit improves the throughput rate by 36% and saves hardware cost by 18% compared with the most representative design based on FPGA. For ASIC implementation, the throughput rate is improved by 75%, and area is decreased by 33%.

Key words: montgomery modular multiplication, modular exponentiation, RSA cryptosystem, VLSI architecture