一种用于人脸检测SoC中的加速协处理器设计

doi:10.3969/j.issn.1001-2400.2011.03.013

Abstract

Abstract:

An improved co-processor architecture suitable for hardware parallel implementation is proposed to perform the feature classification based on the Adaboost algorithm. The co-processor consists of image quick access module, module for calculating the Haar features, DMA data transfer module, and interface to the co-processor module. Modules use the pipeline and FIFO buffer to process data to accelerate the iterative process of face detection. The co-processor only increases a small area in face detection SoC, but significantly improves the speed of face detection. In addition, we implement the proposed SoC on a CYCLONE-Ⅱ EP2C70 FPGA to show that object detection can be achieved at 10 frames per second at the system operating frequency of 70MHz on color QVGA camera video.

Key words: face detection, Adaboost algorithm, features classifiers, co-processor

CLC Number:

TP391

JIAO Jiye；MU Rong；HAO Yue. Co-processor implementation for fast face detection in a system-on-chip[J].J4, 2011, 38(3): 76-82.

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Co-processor implementation for fast face detection in a system-on-chip

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