用于片上网络的准延时不敏感全异步仲裁器

doi:10.3969/j.issn.1001-2400.2011.03.014

Abstract

Abstract:

This paper proposes a quasi delay-insensitive full asynchronous arbiter for the network on chips. With the function of priority self-detection, it improves the quality of service given by the priority variations of data packages from different directions. It can automatically select one of output schemes according to dynamically detecting the changes of priority in data packages, solving the problems of ports priority fixation in the conventional static arbitration mechanism. The stability of arbitration is greatly enhanced owing to decoupling the arbitration module from the output module by locking input requests. The application of the threshold gate makes the whole arbiter quasi delay-insensitive. The arbiter is implemented in 0.18μm standard CMOS technology. Results have shown that the average arbitration time is 1.175ns with average dynamic power consumption of 1.53mW, which can fulfill the demand of high-speed on-chip data package arbitration.

Key words: network on chips, dynamic arbitration, full asynchronous, threshold gate, quasi delay-insensitive

GUAN Xuguang；YANG Yintang；ZHU Zhangming. Quasi delay-insensitive full asynchronous arbiter for the network on chips[J].J4, 2011, 38(3): 83-89.

References

［1］ Shan Yan, Lin B. Custom Networks-on-Chip Architectures with Multicast Routing ［J］. IEEE Trans on Very Large Scale Integration Systems, 2009, 17(3): 342-355.
［2］ Mohsen S, Ali A K, Zainalabedin N. A Low-power High-throughput Link Splitting Router for NoCs ［J］. Journal of Zhejiang University: Science A, 2008, 9(12): 1708-1714.
［3］徐阳扬, 周端, 杨银堂, 等. 非对称GALS系统异步接口设计［J］. 西安电子科技大学学报, 2007, 34(2): 294-297.
Xu Yangyang, Zhou Duan, Yang Yintang, et al. Unsymmetrical Interface Design in GALS ［J］. Journal of Xidian University, 2007, 34(2): 294-297.
［4］杨银堂, 徐阳扬, 周端, 等. 异步超前进位加法器设计［J］. 西安电子科技大学学报, 2009, 36(1): 33-37.
Yang Yintang, Xu Yangyang, Zhou Duan, et al. Design of the Asynchronous CLA Adder ［J］. Journal of Xidian University, 2009, 36(1): 33-37.
［5］ International Technology Roadmap for Semiconductors ［EB/OL］. ［2005-00-00］. Http://www.itrs.net/home.html.
［6］ Dally W J, Towles B. Route Packets, Not Wires: On-Chip Interconnection Networks ［C］//Proc DAC. Las Vegas: IEEE, 2001: 684-689.
［7］ Radu M. On-chip Networks: Two Sides of the Same Coin ［J］. IEEE Design & Test of Computers, 2010, 24(4): 80.
［8］ Martina M, Masera G. Turbo NOC: a Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures ［J］. IEEE Trans on Circuits and Systems, 2010, 57(10): 2776-2789
［9］ Horak M N, Nowick S M, Carlberg M, et al. A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors ［C］//Fourth ACM/IEEE International Symposium on Networks-on-Chip (NOCS). Grenoble: IEEE, 2010: 43-50.
［10］ Feliciian F, Furber S B. An Asynchronous On-chip Network Router with Quality-of-Service (QoS) Support ［C］//Proceedings of IEEE International SOC Conference. Santa Clara: IEEE, 2004: 274-277.
［11］ Zid M, Zitouni A, Baganne A, et al. New Generic GALS NoC Architectures with Multiple QoS ［C］//International Conference on Design and Test of Integrated Systems in Nanoscale Technology. La Marsa: IEEE, 2006: 345-349.
［12］ Rigaud J B, Quartana J, Fesquet L, et al. High-level Modeling and Design of Asynchronous Arbiters For On-chip Communication Systems ［C］//Proceedings of Design, Automation and Test in Europe Conference and Exhibition. Paris: IEEE, 2002: 1090.

Quasi delay-insensitive full asynchronous arbiter for the network on chips

PDF (PC)

Like

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 1

Metrics

Comments

Recommended 10