CAVLC熵编码器的FPGA高效实现

doi:10.3969/j.issn.1001-2400.2012.03.016

Abstract

Abstract:

Since the Context_based Adaptive Variable Length Coding (CAVLC)algorithm in H.264 has both high complexity in computation and great difficulty in real-time implementation, a high efficient architecture for this algorithm is presented. In this design, realization of encoding on different types of data blocks in the block stream sourced from the decomposition of a macro block data conquers the limitation in conventional schemes where only one type of data blocks can be processed. Replacement of zig_zag scan for reverse zig_zag scan in the upstream module results in the elimination of reverse operation and a great rise in efficiency of the CAVLC module with no increase of computation in the upstream module. Finally, results of its verification and realization on FPGA indicate that this structure has as high a maximum coding system frequency as 147.78MHz, the first coding delay of 32 clock cycles, and a throughput delay of 16 clock cycles, thus adequately meeting the requirement for high-definition and real-time applications.

Key words: H.264, CAVLC, entropy encoder, FPGA

CLC Number:

TN919.81

CHU Xiuqin;WU Shuo;CHANG Fang;HE Wenqing. Efficient implementation of the CAVLC entropy encoder based on FPGA[J].J4, 2012, 39(3): 100-105.

References

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Efficient implementation of the CAVLC entropy encoder based on FPGA

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