采用状态度量抽取和内插策略的低功耗Turbo译码器

doi:10.3969/j.issn.1001-2400.2012.03.009

Abstract

Abstract:

A novel forward and backword state metric calculation and the memory management strategy are presencted for the turbo decoder which adopts the Log-MAP(Maximum A-Posteriori) algorithm. By the way of decimating the forward state metric first and then interpolating in the LLR(Log Likelihood Ratio) computation stage to reduce the state metric memory size, which acquires significant power and area benefit with ignorable computation penalty. And the soft in soft out(SISO) scheduling and control mechanism are also addressed for supporting our proposed optimization architecture. Compared with the conventional memory management strategy our design could reduce the state metric size by 80% with the sliding window 128. Based on our proposed architecture an HSDPA turbo decoder is realized by the 65nm CMOS standard cell library with the frequency of 350MHz and the voltage of 1.18V. The result achieves 21.4Mbit/s throughput and 29.3mW power consumption, and an energy efficiency of up to 0.171nJ/bit/iteration.

Key words: Turbo code, max-Log-MAP decoder, static metric decimation and interpolation, VLSI

CLC Number:

TN911.22

LI Xiaofeng;FENG Dazheng;HU Shukai. Low power Turbo decoder based on the state metric decimation and interpolation strategy[J].J4, 2012, 39(3): 58-62+71.

References

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Low power Turbo decoder based on the state metric decimation and interpolation strategy

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