J4 ›› 2012, Vol. 39 ›› Issue (5): 192-196.doi: 10.3969/j.issn.1001-2400.2012.05.032

• Original Articles • Previous Articles    

Compositional verification of a carry-save adder with the propositional projection temporal logic

ZHANG Nan1,2;DUAN Zhenhua1,2   

  1. (1. Inst. of Computing Theory & Technology, Xidian Univ., Xi'an  710071, China;
    2. State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an  710071, China)
  • Received:2012-03-27 Online:2012-10-20 Published:2012-12-13
  • Contact: ZHANG Nan E-mail:nanzhang@stu.xidian.edu.cn

Abstract:

To guarantee the correctness of hardware designs, a compositional methodology for hardware verification is proposed. This methodology uses the propositional projection temporal logic(PPTL) as the underlying logic. The hardware designs(implementations) and properties are formalized with PPTL formulas. The design is correct if the specification can be deduced from the system model in the axiom system of the propositional projection temporal logic. An example for a carry-save adder is given to illustrate the methodology is workable.

Key words: temporal logic, compositional verification, carry-save adder, carry look-ahead adder

CLC Number: 

  • TP301